Highly concurrent DMA controller with programmable DMA channels

1. A computer system comprising:

a mass storage device;

a first data transfer controller for controlling data transfers involving the mass storage device, the first data transfer controller operable in a channel free state and a channel unavailable state;

a circuit device connected to the first data transfer controller, the circuit device for requesting a particular data transfer to be controlled by the first data transfer controller; and

a second data transfer controller connected to the circuit device, the second data transfer controller for controlling data transfers and for controlling the particular data transfer responsive, at least, to the circuit device receiving an indication that the first data transfer controller is in the channel unavailable state.

2. The computer system of claim 1 , wherein the circuit device is a non-host processor entity.

3. The computer system of claim 1 , wherein the circuit device is a microprocessor.

4. The computer system of claim 1 , wherein the second data transfer controller is associated with a memory address and wherein the first data transfer controller, when in the channel unavailable state, is configured to provide the circuit device with the memory address for the second data transfer controller.

5. The computer system of claim 1 , wherein the first data transfer controller includes a storage device for storing an indication of whether the first data transfer controller is in the channel free state or in the channel unavailable state.

6. The computer system of claim 5 , wherein the client is configured to read the indication from the storage device and further wherein responsive to the indication indicating that the first data transfer controller is in the channel unavailable state, request the particular data transfer to be controlled by the second data transfer controller.

7. The computer system of claim 1 , wherein the first data transfer controller is operable in one of a client queuing mode and a channel queuing mode.

8. The computer system of claim 1 , wherein the first data transfer controller is operable in a data streaming mode.

9. The computer system of claim 8 , wherein the first data transfer controller is operable in one of a RAM channel mode and a FIFO channel mode.

10. The computer system of claim 1 , wherein the mass storage device is a hard drive.

11. A data transfer controller for transferring data responsive to a request from a client, the data transfer controller comprising:

a first channel circuitry for providing a first channel for data transfers, the channel circuitry operable in a plurality of modes;

a storage device connected to the first channel circuitry, the storage device for storing an indication of a particular one of the plurality of modes; and

a control circuitry connected to the channel circuitry, the control circuitry for controlling provision of the first channel to the client;

wherein the channel circuitry is operable in the particular one of the plurality of modes, and wherein the first channel is configurable in a one of a client queuing mode and a channel queuing mode, and further wherein the storage device is for storing an indication that the first channel is in one of the client queuing mode and the channel queuing mode.

12. A data transfer controller for transferring data responsive to a request from a client, the data transfer controller comprising:

a first channel circuitry for providing a first channel for data transfers, the channel circuitry operable in a plurality of modes;

a storage device connected to the first channel circuitry, the storage device for storing an indication of a particular one of the plurality of modes; and

a control circuitry connected to the channel circuitry, the control circuitry for controlling provision of the first channel to the client;

wherein the channel circuitry is operable in the particular one of the plurality of modes, and wherein the first channel is configurable in a descriptor stream mode.

13. The data transfer controller of claim 11 included in a memory controller.

14. A DMA controller comprising:

a first channel device for performing in a first DMA transaction, the first channel device operable in a first mode; and

a second channel device for performing a second DMA transaction, the second channel device operable in a second mode;

a first address translation mechanism associated with the first channel device; and

a second address translation mechanism associated with the second channel device, the second address translation mechanism operable independent of the first address translation mechanism;

wherein the first mode and the second mode are different and wherein the first DMA transaction and the second DMA transaction are different.

15. The DMA controller of claim 14 , further comprising a control device connected to the first channel device and the second channel device, the control device for controlling an acquisition of the first channel device responsive to a request for a DMA transaction from a client.

16. The DMA controller of claim 14 , wherein the first mode is one of client queuing mode and channel queuing mode.

17. The DMA controller of claim 14 , wherein the second mode is one of descriptor stream mode, FIFO channel mode and RAM channel mode.

18. A computer system comprising:

a mass storage means;

a first data transfer means for controlling data transfers involving the mass storage means, the first data transfer means operable in a channel free state and a channel unavailable state;

a logical means connected to the first data transfer means, the logical means for requesting a particular data transfer to be controlled by the first data transfer means; and

a second data transfer means connected to the logical means, the second data transfer means for controlling data transfers and for controlling the particular data transfer responsive, at least, to the logical means receiving an indication that the first data transfer means is in the channel unavailable state.

19. The computer system of claim 18 , wherein the second data transfer means is associated with a memory address and wherein the first data transfer means, when in the channel unavailable state, is configured to provide the logical means with the memory address for the second data transfer means.

20. The computer system of claim 18 , wherein the first data transfer means includes a storage means for storing an indication of whether the first data transfer means is in the channel free state or in the channel unavailable state.

21. The computer system of claim 20 , wherein the client is configured to read the indication from the storage means and further wherein responsive to the indication indicating that the first data transfer means is in the channel unavailable state, request the particular data transfer to be controlled by the second data transfer means.

22. The computer system of claim 18 , wherein the first data transfer means is operable in one of a client queuing mode and a channel queuing mode.

23. The computer system of claim 18 , wherein the first data transfer means is operable in a data streaming mode.

24. The computer system of claim 23 , wherein the first data transfer means is operable in one of a RAM channel mode and a FIFO channel mode.

25. A method for transferring data using a controller including a channel, the channel being operable in a plurality of data transfer modes, the method comprising the steps of:

requesting control of the channel;

responsive to receiving control of the channel, configuring the channel to be operable in a particular one of the plurality of modes; and

requesting data to be transferred through the channel, wherein the plurality of data transfer modes includes FIFO channel mode and RAM channel mode.

26. The method of claim 25 , further comprising the step of releasing the control of the channel.

27. A method for transferring data using a controller including a channel, the channel being operable in a plurality of data transfer modes, the method comprising the steps of:

requesting control of the channel;

responsive to receiving control of the channel, configuring the channel to be operable in a particular one of the plurality of modes; and

requesting data to be transferred through the channel, wherein the plurality of data transfer modes includes a software queuing mode and a client queuing mode.

28. A method for transferring data using a controller including a channel, the channel being operable in a plurality of data transfer modes, the method comprising the steps of

requesting control of the channel;

responsive to receiving control of the channel, configuring the channel to be operable in a particular one of the plurality of modes; and

requesting data to be transferred through the channel, wherein the plurality of data transfer modes includes a descriptor streaming mode.