IP Library Assignment 066778/0178
Patent Assignment
Reel/Frame 066778/0178

Assignment of Assignor's Interest

Recorded: 2024-03-09 Pages: 8
Assignor
SONRAI MEMORY LIMITED
Executed: 2024-03-05
Assignee
NERA INNOVATIONS LIMITED
SUITE 23, THE HYDE BUILDING, CARRICKMINES, DUBLIN, 18, IRELAND
Covered Properties (64)
Fuse Data Storage System Using Core Memory
Highly Concurrent Dma Controller with Programmable Dma Channels
Patent: 6,898,646 →
Application: 09/564,341 →
Slack Fetch to Improve Performance in a Simultaneous and Redundantly Threaded Processor
Patent: 6,757,811 →
Application: 09/584,034 →
Simultaneous and Redundantly Threaded Processor Store Instruction Comparator
Patent: 6,854,075 →
Application: 09/837,995 →
Publication: US 2001/0034824
Input Replicator for Interrupts in a Simultaneous and Redundantly Threaded Processor
Patent: 6,792,525 →
Application: 09/838,069 →
Publication: US 2001/0037448
Cycle Count Replication in a Simultaneous and Redundantly Threaded Processor
Patent: 6,854,051 →
Application: 09/839,459 →
Publication: US 2001/0037445
Active Load Address Buffer
Patent: 6,598,122 →
Application: 09/839,621 →
Publication: US 2001/0034827
Simultaneous and Redundantly Threaded Processor Uncached Load Address Comparator and Data Value Replication Circuit
Patent: 6,823,473 →
Application: 09/839,626 →
Publication: US 2001/0034854
Chip Multiprocessor with Multiple Operating Systems
Patent: 6,874,014 →
Application: 09/865,605 →
Publication: US 2002/0184328
Modified Harvard Architecture Processor Having Data Memory Space Mapped to Program Memory Space with Erroneous Execution Protection
Patent: 7,007,172 →
Application: 09/870,460 →
Publication: US 2003/0005245
Error Indication in a Raid Memory System
Patent: 7,028,213 →
Application: 09/965,883 →
Publication: US 2003/0088805
Software Controlled Pre-Execution in a Multithreaded Processor
Patent: 7,343,602 →
Application: 10/029,699 →
Publication: US 2002/0055964
Device Generating a Precise Reference Voltage
Patent: 6,650,175 →
Application: 10/071,605 →
Publication: US 2002/0136065
Memory Auto-Precharge
Patent: 6,832,286 →
Application: 10/179,081 →
Publication: US 2003/0236959
System for Compressing/Decompressing Data
Patent: 6,829,691 →
Application: 10/187,337 →
Publication: US 2004/0003196
Distributed Feedback Laser Device
Patent: 6,912,239 →
Application: 10/206,217 →
Publication: US 2003/0152126
Power-On Reset Circuit
Patent: 6,744,291 →
Application: 10/232,636 →
Publication: US 2004/0041601
Method for Counting Beyond Endurance Limitations of Non-Volatile Memories
Patent: 6,792,065 →
Application: 10/348,782 →
Publication: US 2004/0141580
Variable Charge Pump Circuit with Dynamic Load
Patent: 6,724,241 →
Application: 10/352,733 →
Publication: US 2004/0080360
Portable Ram Drive
Patent: 6,920,527 →
Application: 10/364,583 →
Publication: US 2004/0158674
Temperature-Compensated Current Reference Circuit
Patent: 6,809,575 →
Application: 10/407,622 →
Publication: US 2004/0051580
Integrating Chip Scale Packaging Metallization into Integrated Circuit Die Structures
Patent: 6,917,105 →
Application: 10/453,157 →
Publication: US 2004/0245631
Semiconductor Device Manufacturing Method
Patent: 7,094,620 →
Application: 10/505,180 →
Publication: US 2005/0227477
Regenerative Clock Repeater
Patent: 7,436,232 →
Application: 10/666,142 →
Publication: US 2004/0257131
Differential Charge Pump
Patent: 6,876,244 →
Application: 10/687,980 →
Publication: US 2005/0083090
Integrating Chip Scale Packaging Metallization into Integrated Circuit Die Structures
Patent: 6,900,538 →
Application: 10/760,434 →
Publication: US 2004/0245633
Peripheral Device Feature Allowing Processors to Enter a Low Power State
Patent: 7,159,766 →
Application: 10/762,767 →
Publication: US 2005/0156038
High Frequency Differential Power Amplifier
Patent: 6,937,071 →
Application: 10/802,894 →
Publication: US 2005/0206412
Fuse Data Storage System Using Core Memory
Patent: 7,102,950 →
Application: 10/910,038 →
Publication: US 2006/0023549
Increment/Decrement, Chip Select and Selectable Write to Non-Volatile Memory Using a Two Signal Control Protocol for an Integrated Circuit Device
Patent: 7,199,603 →
Application: 10/946,432 →
Publication: US 2006/0023543
Write Protection Using a Two Signal Control Protocol for an Integrated Circuit Device Having Parameter Change Capability, Chip Select and Selectable Write to Non-Volatile Memory
Patent: 7,091,740 →
Application: 10/954,584 →
Publication: US 2006/0022707
Integrating Chip Scale Packaging Metallization into Integrated Circuit Die Structures
Patent: 7,211,893 →
Application: 10/980,536 →
Publication: US 2005/0062156
Nonvolatile Latch
Patent: 7,336,542 →
Application: 11/049,334 →
Publication: US 2006/0171201
Method and Apparatus for a Dual Power Supply to Embedded Non-Volatile Memory
Patent: 7,120,061 →
Application: 11/061,799 →
Publication: US 2005/0219903
Electric Reference Voltage Generating Device of Improved Accuracy and Corresponding Electronic Integrated Circuit
Patent: 7,218,167 →
Application: 11/062,888 →
Publication: US 2005/0206443
Modified Harvard Architecture Processor Having Data Memory Space Mapped to Program Memory Space with Erroneous Execution Protection
Patent: 7,243,372 →
Application: 11/135,527 →
Publication: US 2005/0210284
Efficient Charge Pump for a Wide Range of Supply Voltages
Patent: 7,259,612 →
Application: 11/168,833 →
Publication: US 2006/0290410
Sense Amplifier Circuit for Parallel Sensing of Four Current Levels
Patent: 7,330,375 →
Application: 11/203,938 →
Publication: US 2006/0256619
Error Indication in a Raid Memory System
Patent: 7,320,086 →
Application: 11/291,243 →
Publication: US 2006/0085671
Method and Apparatus to Prevent High Voltage Supply Degradation for High-Voltage Latches of a Non-Volatile Memory
Patent: 7,369,446 →
Application: 11/457,377 →
Publication: US 2008/0056015
Electrically Disconnecting a Peripheral Device
Patent: 7,325,733 →
Application: 11/530,977 →
Publication: US 2007/0023499
Apparatus for Eliminating Leakage Current of a Low Vt Device in a Column Latch
Patent: 7,453,725 →
Application: 11/539,564 →
Publication: US 2008/0084767
Method and Apparatus for a Dual Power Supply to Embedded Non-Volatile Memory
Patent: 7,450,429 →
Application: 11/539,567 →
Publication: US 2007/0086248
Adaptive Gate Voltage Regulation
Patent: 7,417,904 →
Application: 11/554,797 →
Publication: US 2008/0101133
Amplitude Controlled Sawtooth Generator
Patent: 7,671,642 →
Application: 11/610,107 →
Publication: US 2008/0143394
Differential Amplitude Controlled Sawtooth Generator
Patent: 7,336,110 →
Application: 11/624,139 →
Clock Circuitry for Ddr-Sdram Memory Controller
Patent: 7,423,928 →
Application: 11/668,844 →
Publication: US 2008/0181046
Power Semiconductor Device
Patent: 7,888,733 →
Application: 11/747,503 →
Publication: US 2008/0079069
Method for Enhancing Linearity of a Transistor Amplifier Using Switched Capacitive Loads
Patent: 7,508,266 →
Application: 11/846,959 →
Method and Apparatus to Prevent High Voltage Supply Degradation for High-Voltage Latches of a Non-Volatile Memory
Patent: 7,751,256 →
Application: 11/933,805 →
Publication: US 2008/0056020
Differential Amplitude Controlled Sawtooth Generator
Patent: 7,800,419 →
Application: 12/014,261 →
Publication: US 2008/0174346
Error Detecting/Correcting Scheme for Memories
Patent: 8,112,699 →
Application: 12/031,289 →
Publication: US 2009/0210774
Clock Circuitry for Ddr-Sdram Memory Controller
Patent: 7,679,987 →
Application: 12/207,147 →
Publication: US 2009/0010083
Dual Mode, Single Ended to Fully Differential Converter Structure
Patent: 7,843,232 →
Application: 12/395,518 →
Publication: US 2010/0219864
Cyclic Digital to Analog Converter
Patent: 8,223,056 →
Application: 12/436,620 →
Publication: US 2010/0283651
Circuit and Method for Operating a Circuit
Patent: 8,193,792 →
Application: 12/481,330 →
Publication: US 2009/0302821
Power Semiconductor Device
Patent: 8,421,145 →
Application: 13/042,575 →
Publication: US 2011/0316071
Error Detecting/Correcting Scheme for Memories
Patent: 8,214,729 →
Application: 13/335,725 →
Publication: US 2012/0096334
Circuit and Method for Operating a Circuit
Patent: 8,415,939 →
Application: 13/485,426 →
Publication: US 2012/0236674
Power Semiconductor Device
Patent: 8,829,600 →
Application: 13/753,674 →
Publication: US 2013/0140603
Power Semiconductor Device with Resistance Conterol Structure
Patent: 9,257,542 →
Application: 14/336,774 →
Publication: US 2014/0327040
Analog Feedback Amplifier
Patent: 9,407,216 →
Application: 14/414,283 →
Publication: US 2015/0207476
Frequency Multiplier
Patent: 9,553,568 →
Application: 14/925,344 →
Publication: US 2016/0241221
Multistage Amplifier
Patent: 9,871,493 →
Application: 15/048,340 →
Publication: US 2016/0352288
Related Assignments (17)
Other recorded transfers of the patents in this record — the chain of ownership.
Patent Security Agreement Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
Assignment of Assignor's Interest Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
Termination and Release of Security Interest in Patent Collateral Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
Security Interest Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
Security Interest Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
Security Interest Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
Security Interest Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
Release of Security Interest Dec 21, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 051398/0809 →
Release of Security Interest Dec 21, 2019
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 051398/0827 →
Assignment of Assignor's Interest Feb 4, 2020
From: MICROCHIP TECHNOLOGY INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: SONRAI MEMORY LIMITED
Reel/Frame 051799/0956 →
Assignment of Assignor's Interest Mar 6, 2020
From: MITSUBISHI ELECTRIC CORPORATION
To: ARIGNA TECHNOLOGY LIMITED
Reel/Frame 052042/0651 →
Assignment of Assignor's Interest May 5, 2020
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: SONRAÍ MEMORY, LTD.
Reel/Frame 052567/0734 →
Nunc Pro Tunc Assignment Jul 8, 2020
From: ARIGNA TECHNOLOGY LIMITED
To: SONRAI MEMORY LIMITED
Reel/Frame 053147/0767 →
Release of Security Interest Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059333/0222 →
Release of Security Interest Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
Release of Security Interest Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
Release of Security Interest Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 059358/0001 →