Power semiconductor device

1. A power semiconductor device comprising a semiconductor substrate in which a current flows in a thickness direction of said semiconductor substrate,

wherein said semiconductor substrate includes a resistance control structure disposed in a central portion of said semiconductor substrate having a resistance to current higher than a peripheral portion laterally surrounding said central portion of said semiconductor substrate,

wherein said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type which extends laterally to run across said central portion and said peripheral portion; and

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction and extends laterally to run across said central portion and said peripheral portion;

said second semiconductor layer has a lower impurity concentration in said central portion than said peripheral portion; and

said resistance control structure includes said second semiconductor layer.

2. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type; and

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction;

said second semiconductor layer has a form to be located in said peripheral portion but not located in said central portion; and

said resistance control structure includes said second semiconductor layer.

3. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a lifetime control layer provided in said first semiconductor layer and facing said second semiconductor layer in said thickness direction;

said lifetime control layer has a higher lifetime killer concentration in said central portion than said peripheral portion; and

said resistance control structure includes said lifetime control layer.

4. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type, which faces said first semiconductor layer in said thickness direction; and

a lifetime control layer provided in said first semiconductor layer and facing said second semiconductor layer in said thickness direction;

said lifetime control layer has a form to be located in said central portion but not located in said peripheral portion; and

said resistance control structure includes said lifetime control layer.

5. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a buffer layer of the first conductivity type which is provided between said first semiconductor layer and said second semiconductor layer and has a higher impurity concentration than that of said first semiconductor layer;

said buffer layer has a higher impurity concentration in said central portion than said peripheral portion; and

said resistance control structure includes said buffer layer.

6. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a buffer layer of the first conductivity type which is provided between said first semiconductor layer and said second semiconductor layer and has a higher impurity concentration than that of said first semiconductor layer;

said buffer layer has a form to be located in said central portion but not located in said peripheral portion; and

said resistance control structure includes said buffer layer.

7. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a carrier stored layer of the first conductivity type which faces said first semiconductor layer on a side opposite to said second semiconductor layer in said thickness direction and has a higher impurity concentration than that of said first semiconductor layer;

said carrier stored layer has a lower impurity concentration in said central portion than said peripheral portion; and

said resistance control structure includes said carrier stored layer.

8. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a carrier stored layer of the first conductivity type which faces said first semiconductor layer on a side opposite to said second semiconductor layer in said thickness direction and has a higher impurity concentration than that of said first semiconductor layer;

said carrier stored layer has a form to be located in said peripheral portion but not located in said central portion; and

said resistance control structure includes said carrier stored layer.

9. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type; and

a third semiconductor layer of the first conductivity type which faces said first semiconductor layer in said thickness direction and has a higher impurity concentration than that of said first semiconductor layer;

said first semiconductor layer and said third semiconductor layer configure a drift layer and a drain layer of a MISFET, respectively;

said drain layer has a lower impurity concentration in said central portion than said peripheral portion; and

said resistance control structure includes said drain layer.

10. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type; and

a third semiconductor layer of the first conductivity type which faces said first semiconductor layer in said thickness direction and has a higher impurity concentration than that of said first semiconductor layer;

said first semiconductor layer and said third semiconductor layer configure a drift layer and a drain layer of a MISFET, respectively;

said drain layer has a form to be located in said peripheral portion but not located in said central portion; and

said resistance control structure includes said drain layer.

11. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes a plurality of switching elements having a MIS structure and controlling on/off of said current;

said MIS structure includes a channel formation semiconductor layer being a semiconductor layer in which a channel is formed and having a higher impurity concentration in said central portion than said peripheral portion; and

said resistance control structure includes said channel formation semiconductor layer.

12. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a third semiconductor layer of the first conductivity type which faces said first semiconductor layer on a side opposite to said second semiconductor layer in said thickness direction and has a higher impurity concentration than that of said first semiconductor layer;

said second semiconductor layer and said third semiconductor layer configure an anode layer and a cathode layer of a diode, respectively;

said cathode layer has a lower impurity concentration in said central portion than said peripheral portion; and

said resistance control structure includes said cathode layer.

13. The power semiconductor device according to claim 1 , wherein:

said semiconductor substrate includes:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type which faces said first semiconductor layer in said thickness direction; and

a third semiconductor layer of the first conductivity type which faces said first semiconductor layer on a side opposite to said second semiconductor layer in said thickness direction and has a higher impurity concentration than that of said first semiconductor layer;

said second semiconductor layer and said third semiconductor layer configure an anode layer and a cathode layer of a diode, respectively;

said cathode layer has a form to be located in said peripheral portion but not located in said central portion; and

said resistance control structure includes said cathode layer.

14. The power semiconductor device according to claim 1 , wherein:

said resistance control structure comprises a layer in said substrate.

15. The power semiconductor device according to claim 1 , comprising:

an insulated gate bipolar transistor structure having a base layer, emitter layer and a collector layer,

said resistance control structure being disposed in said collector layer.

16. The power semiconductor device according to claim 1 , comprising:

an insulated gate bipolar transistor structure having a base layer in which a channel region is formed,

said central portion of said resistance control structure being located directly under said channel region in said base layer.

17. The power semiconductor device according to claim 1 , comprising:

said central portion having a lower injection efficiency of holes than said peripheral portion.