Dual mode, single ended to fully differential converter structure
View Patent ↗A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode.
1. A dual mode, single ended to fully differential converter structure, comprising:
a differential amplifier having a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, the positive output terminal of the differential amplifier coupled to the negative input terminal of the differential amplifier through a first feedback capacitor, the positive input terminal and negative output terminal coupled to a first bypass switch which is operable for bypassing the first feedback capacitor during a sampling phase, the negative output terminal of the differential amplifier coupled to the positive input terminal of the differential amplifier through a second feedback capacitor, the negative input terminal and positive output terminal of the differential amplifier coupled to a second bypass switch which is operable for bypassing the second feedback capacitor during the sampling phase;
a first node coupled to a positive input terminal of the converter structure, a first switch, a second switch, a third switch and to a first terminal of a first sampling capacitor, the first switch operable for coupling the positive input terminal of the converter structure to the first node during the sampling phase, the second switch operable for coupling a reference voltage to the first node during the sampling phase, the third switch operable for coupling a common mode voltage to the first node during a transferring phase which occurs after the sampling phase;
a second node coupled to a second terminal of the first sampling capacitor, a fourth switch, a fifth switch and a sixth switch, the fourth switch operable for coupling the positive input terminal of the differential amplifier to the second node during the transferring phase, the fifth switch operable for coupling the reference voltage to the second node during the sampling phase, the sixth switch operable for coupling a negative input terminal of the converter structure to the second node during the sampling phase;
a third node coupled to the negative input terminal of the converter structure, a seventh switch, an eighth switch, a ninth switch and to a first terminal of a second sampling capacitor, the seventh switch operable for coupling the negative input terminal of the converter structure to the third node during the sampling phase, the eighth switch operable for coupling the reference voltage to the third node during the sampling phase, the ninth switch operable for coupling the common mode voltage to the third node during the transferring phase; and
a fourth node coupled to a second terminal of the second sampling capacitor, a tenth switch, a eleventh switch and a twelfth switch, the tenth switch operable for coupling the negative input terminal of the differential amplifier to the fourth node during the transferring phase, the eleventh switch operable for coupling the reference voltage to the fourth node during the sampling phase, the twelfth switch operable for coupling the positive input terminal of the converter structure to the fourth node during the sampling phase.
2. The converter of claim 1 , where the switches are CMOS switches.
3. The converter of claim 1 , further comprising:
an analog-to-digital converter coupled to at least one of the positive and negative outputs of the differential amplifier.