Granted Patent B2

US 7,120,061 · App. 11/061,799 · Granted Oct 10, 2006

Abstract

Claims (48)

1. An embedded non-volatile memory being driven at an external voltage level and at an regulated voltage level, the external voltage level higher than the regulated voltage level, comprising:

a charge pump configured to receive the external voltage level and generate a high voltage level, the high voltage level higher than the external voltage level;

a memory control circuit coupled to the charge pump and configured to receive the external voltage level and the high voltage level, and further configured to select between and provide the external and the high voltage levels;

a memory array, having a word line and a bit line, coupled to the memory control circuit and configured to store data and to receive the external and high voltage levels at the word line, and to receive the high voltage levels at the bit line;

a word line driver coupled to the memory array and configured to provide the external and high voltage levels to the word line;

a bit line selector coupled to the memory array and configured to select the bit line and receive the high, external, and regulated voltage levels; and

a bit line driver coupled to the bit line selector and configured to provide the external and regulated voltage levels to the bit line selector.

2. The memory of claim 1 wherein the memory control circuit further comprises:

a variable voltage line configured to supply the high and external voltage levels;

a first transistor coupled to the variable voltage line and configured to receive the external voltage level and convey the external voltage level to the variable voltage line; and

a level shifter coupled to the first transistor and configured to receive a read signal and assert the first transistor when the read signal indicates a memory read and deassert the first transistor when the read signal does not indicate a memory read, wherein the first transistor conveys the external voltage level to the variable voltage line during the memory read, otherwise the variable voltage line conveys the high voltage level.

3. The memory of claim 2 further comprising:

a second transistor having a drain coupled to the variable voltage line, a gate coupled to the level shifter, and a source coupled to a gate of the first transistor; and

a third transistor having a drain coupled to the source of the second transistor and the gate of the first transistor, a source coupled to a ground potential, and a gate coupled to the level shifter, wherein the first and second transistors are configured to assert the first transistor when the read signal indicates a memory read and deassert the first transistor when the read signal does not indicate a memory read.

4. The memory of claim 3 further comprising:

an inverter having an input configured to receive the read signal and an output coupled to the level shifter.

5. The memory of claim 1 wherein the word line driver further comprises:

a variable voltage line configured to supply the high and external voltage levels;

a first transistor coupled to the variable voltage line and to the word line and configured to receive the external and high voltage levels and convey the external and high voltage levels to the word line; and

a second transistor coupled to the word line and configured to receive a control signal and assist in bringing the word line toward the regulated voltage level when the control signal indicates a memory read, wherein the first transistor conveys the external voltage level to the word line during a memory read, and the first transistor conveys the high voltage level to the word line during a memory write.

6. The memory of claim 5 further comprising:

a word select input coupled to the second transistor and configured to convey a word line select signal;

a level shifter coupled to the word select input, the variable voltage line and a gate of the first transistor, the level shifter configured to assert the first transistor if the level shifter received the word line select signal and otherwise deassert the first transistor.

7. The memory of claim 6 wherein the first transistor further comprises a drain coupled to the variable voltage line and a source coupled to the word line, and the second transistor further comprises a drain coupled to the word select input and a source coupled to the word line and a gate configured to receive the control signal.

8. The memory of claim 7 wherein the word line select signal is at the regulated voltage level.

9. The memory of claim 8 wherein the second transistor, during the memory read, is further configured to supply current to the word line until the word line reaches the regulated voltage level minus the threshold voltage of the second transistor, and then stop supplying current as voltage on the word line rises to the external voltage level.

10. The memory of claim 1 wherein the bit line selector further comprises:

a first transistor coupled to the bit line and configured to receive the high voltage level during a memory write and to receive the external voltage level during a memory read; and

a second transistor coupled to the first transistor and a sense line, and configured to receive the regulated voltage level during a memory read.

11. The memory of claim 10 wherein the first transistor further comprises a drain coupled to the bit line and configured to receive the high voltage level during the memory write, a gate configured to receive the external voltage level, and a source.

12. The memory of claim 11 wherein the second transistor further comprises a drain coupled to the source of the first transistor, a gate configured to receive the regulated voltage level, and a drain coupled to the sense line.

13. The memory of claim 12 further comprising a predecoder configured to receive an address and output the regulated voltage level to the gate of the second transistor.

14. The memory of claim 13 wherein the bit line driver further comprises a level shifter coupled to the predecoder and configured to receive the regulated voltage level from the predecoder and output the external voltage level to the gate of the first transistor.

15. The memory of claim 1 further comprising:

a predecoder configured to receive an address and output the regulated voltage level; and

wherein the bit line driver further comprises a level shifter coupled to the predecoder and configured to receive the regulated voltage level from the predecoder and output the external voltage level.

16. A method of driving an embedded non-volatile memory, having a word line and a bit line, at an external voltage level and at an regulated voltage level, the external voltage level higher than the regulated voltage level comprising:

boosting the external voltage level to a high voltage level, the high voltage level higher than the external voltage level;

supplying the high voltage level to a variable voltage line during a memory write; and

supplying the external voltage level to the variable voltage line during a memory read.

17. The method of claim 16 , further comprising:

switching the high voltage level from the variable voltage line to the word line during the memory write; and

switching the external voltage level from the variable voltage line to the word line during the memory read.

18. The method of claim 17 , further comprising:

precharging the word line with the regulated voltage level during the memory read.

19. The method of claim 18 , further comprising:

turning on a transistor in a bit line selector with the external voltage level; and

turning on a second transistor in the bit line selector with the regulated voltage level.

Assignments (12)