Integrating chip scale packaging metallization into integrated circuit die structures
View Patent ↗Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.
1. An integrated circuit structure including chip-scale packaging, the structure comprising:
plurality of active elements in a surface of a semiconductor die;
at least one conductive-material bus electrically interconnecting said active elements;
said chip-scale packaging including at least one, conductive-material, input-output bump extending outwardly from said die for electrically connecting said plurality of active elements to off-die electronics, and a beam of conductive material connecting said bus to said bump;
said bus having a construction wherein the conductive material forming said beam is extended to regions of said structure for thickening of said bus such that resistance of said bus is reduced, and
said plurality of active elements comprises at least one row of MOSFET drain regions adjacent at least one row of MOSFET source regions,
each row of MOSFET drain regions having a first said bus leading to a first input-output pad, said first input-output pad having a first said beam leading to a first said input-output bump, and
each row of MOSFET drain regions having second bus leading to a second input-output pad, said second input-output pad having a first said beam leading to a second said input-output bump,
wherein said conductive-material of said first beam extends superjacently said first said bus and said conductive-material of said second beam extends superjacently said second said bus and
wherein for a predetermined (R ON ) * Area figure-of-merit for said structure, lateral footprint area is reduced in direct relationship to reduction of R ON by said thickening of the bus.
2. The structure as set forth in claim 1 wherein said active elements comprise rows of respective source regions and respective drain regions in said surface, forming an array of MOSFETs, each of said rows having a said bus.
3. The structure as set forth in claim 2 wherein for a given area of said surface, a (R ON ) * Area figure-of-merit for said structure is improved by a factor in the approximate range of at least ten percent to thirty percent over known manner structures.
4. The structure as set forth in claim 2 wherein for a predetermined specification for R ON , lateral footprint area of said structure is reduced by a factor in the approximate range of approximately ten to thirty percent over known manner structures.
5. The structure as set forth in claim 1 wherein said plurality of active elements comprises poles of discrete elements.
6. The structure as set forth in claim 1 wherein said plurality of active elements comprises regions of MOSFETs.
7. The structure as set forth in claim 1 wherein said plurality of active elements comprises regions of bipolar transistors.
8. The structure as set forth in claim 1 further comprising:
said plurality of active elements comprises at least one row of MOSFET drain regions adjacent at least one row of MOSFET source regions,
each row of MOSFET drain regions having a first said bus leading to a first input-output pad, said first input-output pad having a first said beam leading to a first said input-output bump, and
each row of MOSFET drain regions having a second said bus leading to a second input-output pad, said second input-output pad having a first said beam leading to a second said input-output bump,
wherein said conductive-material of said first beam extends superjacently said first said bus and said conductive-material of said second beam extends superjacently said second said bus.
9. The structure as set forth in claim 1 wherein for a predetermined R ON characteristic and lateral footprint area for said structure, by said thickening of the bus, a measurement-of-performance calculated as (R ON ) * Area is substantially lowered.