Clock circuitry for DDR-SDRAM memory controller
View Patent ↗A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.
1. A circuit for providing delayed clock signals to synchronous memory controller, comprising:
a phased locked loop circuit to generate a faster clock from an original clock signal;
a logic delay circuit to performing a synchronous memory device read access, the logic delay circuit to generate delay interval information to apply to a control signal sent to a synchronous memory device;
a programmable delay line to receive the delay interval information from the logic delay circuit and to output a delayed clock signal that has the same frequency and waveform as the clock signal provided to the synchronous memory device, the programmable delay line including an output to provide the delayed clock signal; and
the logic delay circuit to generate a signal delay of a clock period of the clock signal sent to the synchronous memory device.
2. The circuit of claim 1 , wherein the programmable delay is part of a micro-controller circuit.
3. The circuit of claim 1 , wherein the programmable delay is to drive a double data rate memory controller.
4. The circuit of claim 1 , wherein the logic delay circuitry comprises an up/down counter circuit to change the delay interval amount.
5. The circuit of claim 1 , wherein the signal delay of the clock period is a configurable amount.
6. The circuit of claim 1 , wherein the logic delay circuit comprises a lookup table that sets the fractional coefficient number to assist setting the signal delay of the clock period.
7. The circuit of claim 1 , wherein the logic delay circuitry comprises a delayed locked loop.
8. The circuit of claim 1 , wherein the clock signal is to be applied to a double data rate memory.
9. The circuit of claim 2 , wherein the micro-controller circuit is driven with a different frequency clock from the synchronous memory controller.
10. The circuit of claim 9 , where the programmable delay line receives the delay interval information from a delay circuit using a programmable delay line to delay a control signal received from the synchronous memory controller during read access.
11. The circuit of claim 1 , wherein the logic delay circuit is to generate a signal delayed by approximately ¼ of the clock period of the clock signal.
12. The circuit of claim 1 , wherein the logic delay circuit is to generate delay interval information for a DQS signal for a DDR-SDRAM.