Granted Patent B2

US 7,336,542 · App. 11/049,334 · Granted Feb 26, 2008

Abstract

Claims (22)

1. A nonvolatile latch comprising:

a memory element for storing an input data value; and

a write protect element coupled to the memory element, the write protect element comprising a power source circuit coupled to a clock disable circuit and utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the nonvolatile latch.

2. The nonvolatile latch of claim 1 wherein the power source circuit provides a power source signal to the memory element when the write protect signal is in a first state.

3. The nonvolatile latch of claim 2 wherein the clock disable circuit disables a clock signal internally when the write protect signal is in the first state.

4. The nonvolatile latch of claim 3 wherein conventional latch operation occurs when the write protect signal is in a second state.

5. The nonvolatile latch of claim 4 wherein the write protect signal is in the second state when the supply voltage is regained.

6. A method for achieving nonvolatile data storage in a latch, the method comprising:

storing an input data value in a latch memory element; and

utilizing a write protect signal in a latch write protect element to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the latch, wherein the latch write protect circuit comprises a power source circuit coupled to a clock disable circuit.

7. The method of claim 6 further comprising providing a power source signal from the power source circuit to the latch memory element when the write protect signal is in a first state.

8. The method of claim 7 further comprising disabling a clock signal internally through the clock disable circuit when the write protect signal is in the first state.

9. The method of claim 8 further comprising resuming conventional latch operation with the write protect signal in a second state when the supply voltage is regained.

10. A latch capable of nonvolatile operation, the latch comprising:

an input element for receiving an input data value;

a memory element coupled to the input element for storing the input data value;

a write protect element coupled to the memory element, the write protect element comprising a power source circuit coupled to a clock disable circuit and utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the latch; and

an output element coupled to the memory element for outputting a stored data value.

11. The latch of claim 10 wherein the power source circuit provides a power source signal to the memory element when the write protect signal is in a first state.

12. The latch of claim 11 wherein the clock disable circuit disables a clock signal internally when the write protect signal is in the first state.

13. The latch of claim 12 wherein conventional latch operation occurs when the write protect signal is in a second state.

14. The latch of claim 13 wherein the write protect signal transitions to the second state when the supply voltage is regained.

Assignments (12)