IP Library Granted Patent US 8,193,792
Granted Patent B2
US 8,193,792 · App. 12/481,330 · Granted Jun 5, 2012

Circuit and method for operating a circuit

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Quick Facts
Patent No.
US 8,193,792
App. No.
12/481,330
Granted
Jun 5, 2012
Kind
B2
Abstract

A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.

Claims (43)

1. A circuit comprising:

a first voltage regulator;

a second voltage regulator; and

a circuit section, the circuit section comprising a memory element and operable to:

receive a supply voltage from the first voltage regulator when in an operating mode;

transition from the operating mode to a sleep mode, the transition comprising deactivation of inputs of the circuit section; and

receive a standby voltage from the second voltage regulator when in the sleep mode, the standby voltage being less than the supply voltage and sufficient to preserve an information item stored in the memory element.

2. The circuit of claim 1 , further comprising a switching device operable to:

receive a control signal from the first voltage regulator; and

deactivate the inputs of the circuit section in response to the control signal.

3. The circuit of claim 1 , further comprising a switching device operable to:

receive a control signal from the circuit section; and

deactivate the first voltage regulator in response to the control signal.

4. The circuit of claim 1 , wherein the circuit section is operable to transition from the sleep mode to the operating mode.

5. The circuit of claim 1 , further comprising:

an additional circuit section; and

a switch connectable to the additional circuit section and to the second voltage regulator, the switch in a state for the sleep mode configured to separate the additional circuit section from the second voltage regulator.

6. The circuit of claim 5 , wherein the first voltage regulator comprises a control loop connectable through a voltage divider to a supply voltage output of the first voltage regulator.

7. The circuit of claim 1 , further comprising a reset device configured to issue reset signals for resetting the circuit section.

8. The circuit of claim 7 , wherein the reset device is connectable to the first voltage regulator and is configured to activate the first voltage regulator upon an initial application of an input voltage to the circuit.

9. The circuit of claim 7 , wherein the reset device is configured to enable an activation of the first voltage regulator by the circuit section.

10. A method comprising:

delivering to a circuit section of a circuit a supply voltage from a first voltage regulator when in an operating mode;

transitioning from the operating mode to a sleep mode, the transition comprising deactivation of inputs of the circuit section; and

delivering to the circuit section a standby voltage from a second voltage regulator when in the sleep mode, the standby voltage being less than the supply voltage and sufficient to preserve an information item stored in a memory element.

11. The method of claim 10 , comprising:

receiving a control signal from the first voltage regulator; and

deactivating the inputs of the circuit section in response to the control signal.

12. The method of claim 10 , comprising:

receiving a control signal from the circuit section; and

deactivating the first voltage regulator in response to the control signal.

13. The method of claim 10 , further comprising transitioning from the sleep mode to the operating mode.

14. The method of claim 10 , wherein the circuit comprises:

an additional circuit section; and

a switch connectable to the additional circuit section and to the second voltage regulator, the switch in a state for the sleep mode configured to separate the additional circuit section from the second voltage regulator.

15. The method of claim 14 , wherein the first voltage regulator of the first and second voltage regulators has a control loop, the control loop connectable to a supply voltage output of the first voltage regulator through a voltage divider.

16. The method of claim 10 comprising issuing a reset signal for resetting the circuit section.

17. The method of claim 16 comprising activating the first voltage regulator upon an initial application of an input voltage to the circuit.

18. The method of claim 16 comprising enabling an activation of the first voltage regulator by the circuit section.

19. A circuit comprising:

means for delivering to a circuit section a supply voltage from a first voltage regulator when in an operating mode;

means for transitioning from the operating mode to a sleep mode, the transition comprising deactivation of inputs of the circuit section; and

means for delivering to the circuit section a standby voltage from a second voltage regulator when in the sleep mode, the standby voltage being less than the supply voltage and sufficient to preserve an information item stored in a memory element.

Assignments (14)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2024
From: SONRAI MEMORY LIMITED
To: NERA INNOVATIONS LIMITED
Reel/Frame 066778/0178 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2020
From: MICROCHIP TECHNOLOGY INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: SONRAI MEMORY LIMITED
Reel/Frame 051799/0956 →
RELEASE OF SECURITY INTEREST Recorded Dec 21, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 051398/0809 →
RELEASE OF SECURITY INTEREST Recorded Dec 21, 2019
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 051398/0827 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2011
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 025899/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2009
From: KLUGE, WOLFRAM; ZARBOCK, JEANNETTE; FERCHLAND, TILO
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 022801/0523 →