Granted Patent B1

US 6,874,110 · App. 09/569,741 · Granted Mar 29, 2005

Abstract

Claims (37)

1. A self-testing programmable logic array (PLA) system, comprising:

an array of programmably interconnected logic cells;

a built-in self-test (BIST) structure interconnected with the logic cells; and

a BIST engine having an initiation input;

characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test memory of the logic cells, programmable interconnections between the logic cells, and functional logic of the logic cells of the self-testing PLA system and wherein the programmable logic cells of the array of programmable interconnected logic array includes logic cells arranged along lines and are addressed by an address line, the BIST structure including at least:

a sample line sampling outputs of programmable logic cells,

a vector line for sending an input vector to programmable logic cells,

a force line controlling whether the input vector is sent to the programmable logic cells, and

a plurality of compare blocks wherein each compare block is associated with a different one of the lines and comprises:

an element for controlling the sample line and the force line;

an element for address decoding that generates address line signals; and

a compare element for comparing outputs of programmable logic cells.

2. The self-testing PLA system of claim 1 , the compare block further comprises an element including program logic.

3. A self-testing programmable logic array (PLA) system, comprising:

an array of programmably interconnected logic cells;

a built-in self-test (BIST) structure interconnected with the logic cells; and

a BIST engine having an initiation input;

characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test memory of the logic cells, programmable interconnections between the logic cells, and functional logic of the logic cells of the self-testing PLA system wherein the programmable logic cells of the array of interconnected programmable logic cells having memory data, the self-testing PLA system further comprising:

an element including program logic;

a sample line for sampling outputs of the programmable logic cells;

a vector line for sending an input vector to programmable logic cells;

a force line controlling whether the input vector is sent to the programmable logic cells; and

an element for controlling the sample line and controlling the force line.

4. The self-testing PLA system of claim 3 further comprising a bit line connecting the programmable logic cell to the elements including program logic and to the elements for controlling the sample line and controlling the force line.

5. The self-testing PLA system of claim 3 further comprising a global line that interconnect the programmable logic cells to perform a logical function and connect the programmable logic cells to the element for controlling the sample line and controlling the force line, the global line is driven by he vector signal.

6. The self-testing PLA system of claim 3 further comprising an address lines connecting the element for address decoding to the element controlling a sample line and controlling a force line.

7. A self-testing programmable logic array (PLA) system, comprising:

an array of programmably interconnected logic cells;

a built-in self-test (BIST) structure interconnected with the logic cells; and

a BIST engine having an initiation input;

characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test memory of the logic cells, programmable interconnections between the logic cells, and functional logic of the logic cells of the self-testing PLA system wherein each programmable logic cell of the array of interconnected programmable logic cells comprises:

circuitry for performing logic functions;

memory cells for controlling the configuration of the circuitry for performing logic functions;

an input for decoding signals from x and y address lines;

an input for a global x line;

an input for a global y line; and

an input for a bit line for writing to the memory cells.

Assignments (6)