IP Library Assignment 036416/0211
Patent Assignment
Reel/Frame 036416/0211

Assignment of Assignor's Interest

Recorded: 2015-08-25 Pages: 7
Assignor
EXAR CORPORATION
Executed: 2015-06-26
Assignee
XILINX, INC.
2100 LOGIC DRIVE, SAN JOSE, CALIFORNIA, 95124
Covered Properties (23)
Multi-Scale Programmable Array
Patent: 6,633,181 →
Application: 09/475,400 →
Carry Lookahead for Programmable Logic Array
Patent: 6,426,648 →
Application: 09/550,919 →
Apparatus and Method for Self Testing Programmable Logic Arrays
Patent: 6,874,110 →
Application: 09/569,741 →
Efficient and robust random access memory cell suitable for programmable logic configuration control
Patent: 6,292,388 →
Application: 09/606,791 →
Multi-Scale Programmable Array
Patent: 7,062,520 →
Application: 09/883,976 →
Publication: US 2001/0049816
Efficient and Robust Random Access Memory Cell Suitable for Programmable Logic Configuration Control
Patent: 6,418,045 →
Application: 09/896,406 →
Publication: US 2002/0001222
Design Methodology for Merging Programmable Logic into a Custom Ic
Patent: 6,857,110 →
Application: 10/067,151 →
Programmable Logic Core Adapter
Patent: 6,744,274 →
Application: 10/206,872 →
Transitive Processing Unit for Performing Complex Operations
Patent: 7,269,616 →
Application: 10/394,824 →
Publication: US 2004/0186872
System and Method for Efficiently Mapping Heterogeneous Objects Onto an Array of Heterogeneous Programmable Logic Resources
Patent: 7,000,211 →
Application: 10/404,680 →
Publication: US 2004/0194048
Extension Adapter
Patent: 7,590,829 →
Application: 10/404,706 →
Publication: US 2004/0193852
Defining Instruction Extensions in a Standard Programming Language
Patent: 7,373,642 →
Application: 10/630,542 →
Publication: US 2005/0027971
Instruction Set for Efficient Bit Stream and Byte Stream I/O
Patent: 7,421,561 →
Application: 10/686,882 →
Publication: US 2005/0027944
Reconfigurable Instruction Set Computing
Patent: 6,954,845 →
Application: 10/732,392 →
Publication: US 2005/0027970
Systems and Methods for Software Extensible Multi-Processing
Patent: 7,581,081 →
Application: 10/750,714 →
Publication: US 2004/0250046
Configuring a Multi-Processor System
Patent: 8,001,266 →
Application: 10/815,453 →
System, Apparatus and Method for Data Path Routing Configurable to Perform Dynamic Bit Permutations
Patent: 7,237,055 →
Application: 10/931,491 →
System, Apparatus and Method for Implementing Multifunctional Memory in Reconfigurable Data Path Processing
Patent: 7,526,632 →
Application: 10/971,372 →
Systems and Methods for Selecting Input/Output Configuration in an Integrated Circuit
Patent: 7,613,900 →
Application: 11/021,247 →
Publication: US 2005/0114565
Video Processing System with Reconfigurable Instructions
Patent: 7,284,114 →
Application: 11/099,280 →
Publication: US 2005/0169550
Long Instruction Word Processing with Instruction Extensions
Patent: 7,418,575 →
Application: 11/129,146 →
Publication: US 2006/0259747
Programmable Logic Configuration for Instruction Extensions
Patent: 7,610,475 →
Application: 11/204,555 →
Publication: US 2005/0273581
System, Apparatus and Method for Data Path Routing Configurable to Perform Dynamic Bit Permutations
Patent: 7,620,764 →
Application: 11/768,113 →
Publication: US 2007/0250656
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest Mar 9, 2015
From: STIFEL FINANCIAL CORP.
To: EXAR CORPORATION; CADEKA MICROCIRCUITS, LLC
Reel/Frame 035168/0384 →