IP Library Granted Patent US 7,610,475
Granted Patent B2
US 7,610,475 · App. 11/204,555 · Granted Oct 27, 2009

Programmable logic configuration for instruction extensions

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Quick Facts
Patent No.
US 7,610,475
App. No.
11/204,555
Granted
Oct 27, 2009
Kind
B2
Abstract

A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Claims (12)

1. A processing system with reconfigurable instruction extensions, the system comprising: a processor operable to execute a computer program comprising a set of computational instructions and at least one instruction extension; programmable logic operable to receive configuration information to configure the programmable logic for the instruction extension and operable to execute the instruction extension; an extension adapter coupled to the processor, the extension adapter operable to: detect an instruction extension issued by the processor, detect a residency of the issued instruction extension in the programmable logic, and communicate an exception to the processor based on residency of the issued instruction extension in the programmable logic; the processor operable to issue a fault to the operating system in response to the exception; a register file coupled to the programmable logic and operable to store data; and a load/store module operable to transfer the data directly between the register file and a system memory.

2. The processing system of claim 1 wherein the extension adapter is operable to detect residency of the instruction extension in the programmable logic based on contents of a resident instruction table in the extension adapter.

3. The processing system of claim 1 wherein the processor is operable to execute a computer program comprising a set of computational information to load the configuration information into the extension adapter.

4. The processing system of claim 2 wherein the extension adapter is operable to load the configuration information into the programmable logic.

5. The processing system of claim 4 wherein the processor is operable to initiate loading of configuration information into the extension adapter concurrently with the execution of a computer program using direct memory access.

6. The processing system of claim 1 wherein the extension adapter is operable to detect whether the programmable logic is busy executing another instruction extension and wait until the programmable logic is finished executing the another instruction extension.

7. The processing system of claim 1 wherein the extension adapter is operable to determine whether a stored state exists for the instruction extension and restore the stored state in the programmable logic for the instruction extension.

8. The processing system of claim 7 wherein the extension adapter is operable to store the stored state for the instruction extension.

9. The processing system of claim 1 further comprising configuration memory operable to store configuration information for the programmable logic.

10. The processing system of claim 4 wherein the processor is operable to load configuration information into the extension adapter.

11. The processing system of claim 1 wherein a computer program initiates a load of configuration information into the programmable logic.

12. The processing system of claim 1 wherein a computer program initiates a load of configuration information into the programmable logic using a system call.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2015
From: EXAR CORPORATION
To: XILINX, INC.
Reel/Frame 036416/0211 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2015
From: STIFEL FINANCIAL CORP.
To: EXAR CORPORATION; CADEKA MICROCIRCUITS, LLC
Reel/Frame 035168/0384 →
SECURITY INTEREST Recorded May 29, 2014
From: EXAR CORPORATION; CADEKA MICROCIRCUITS, LLC
To: STIFEL FINANCIAL CORP.
Reel/Frame 033062/0123 →
ACQUISITION Recorded Feb 20, 2014
From: STRETCH, INC.
To: EXAR CORPORATION
Reel/Frame 032301/0591 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jan 15, 2014
From: MMV CAPITAL PARTNERS INC., AS ASSIGNEE OF MMV FINANCE INC.
To: STRETCH, INC.
Reel/Frame 032037/0551 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jan 15, 2014
From: SILICON VALLEY BANK
To: STRETCH, INC.
Reel/Frame 032037/0527 →
SECURITY AGREEMENT Recorded Jan 8, 2013
From: STRETCH, INC.
To: MMV FINANCE INC.
Reel/Frame 029591/0364 →
SECURITY AGREEMENT Recorded Nov 29, 2010
From: STRETCH, INC.
To: SILICON VALLEY BANK
Reel/Frame 025413/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2005
From: ARNOLD, JEFFREY MARK; BANTA, GARELD HOWARD; JOHNSON, SCOTT DANIEL; WANG, ALBERT R.
To: STRETCH, INC.
Reel/Frame 016875/0875 →