Instruction set for efficient bit stream and byte stream I/O
View Patent ↗A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.
1. A method of processing data, the method comprising:
receiving a sequence of aligned data, the aligned data being aligned relative to a memory;
receiving a user defined instruction;
loading unaligned data which is a subset of the sequence of aligned data into a programmable instruction set extension fabric;
executing the user defined instruction using the unaligned data to create an unaligned instruction output;
receiving the unaligned instruction output;
aligning unaligned instruction output to the memory to create aligned data; and
storing the aligned data in the memory.
2. The method of claim 1 , wherein receiving the sequence of aligned data is controlled by a processor using a load/store instruction, and the user defined instruction is received from the processor.
3. The method of claim 1 , wherein the sequence of aligned data is received from a first location within the memory and the aligned data is written to a second different location within the memory.
4. A method for processing data sequences in a computing system, the method comprising:
initializing a load/store buffer in an extension adapter by loading a first aligned word into a load/store buffer;
further initializing the load/store buffer by loading a second aligned word into the load/store buffer, alignment of the first aligned word and the second aligned word being relative to a memory accessible via a processor;
reading an unaligned data sequence from the load/store buffer into a register file of an extension adapter for use by an instruction received from the processor, the unaligned data sequence including at least part of the second aligned word;
loading additional aligned words to the load/store buffer to replace the first aligned word and the second aligned word;
executing the unaligned data sequence; and
changing a memory address pointer by an amount less than a length of the second aligned word to point to a next unaligned data sequence to be read.
5. The method of claim 4 , wherein each of the data sequences has a length of one byte.
6. The method of claim 4 , wherein each of the data sequences has a length of one bit.
7. The method of claim 4 , wherein the instruction received from the processor is a member of an extensible instruction set.
8. The method of claim 4 , wherein each unaligned data sequence has a length less than a length of the second aligned word.