Chip package with capacitor
View Patent ↗A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.
1. A chip package comprising:
a circuit substrate;
a first chip over said circuit substrate;
a second chip over said circuit substrate;
a first bump under said circuit substrate;
a second bump under said circuit substrate;
a third bump between said first chip and said circuit substrate, wherein said third bump has a height less than that of said first bump; and
a first passive device under said circuit substrate, wherein said first passive device is between said first and second bumps.
2. The chip package of claim 1 , wherein said first passive device is under said first chip.
3. The chip package of claim 1 further comprising a fourth bump connecting said second chip and said circuit substrate.
4. The chip package of claim 1 further comprising a second passive device over said circuit substrate.
5. The chip package of claim 1 , wherein said first passive device comprises a capacitor.
6. The chip package of claim 1 , wherein said circuit substrate comprises a printed circuit board.
7. The chip package of claim 1 , wherein said first bump comprises solder.
8. The chip package of claim 1 , wherein said first bump comprises solder, and said second bump comprises solder.
9. The chip package of claim 1 , wherein the distance between said first passive device and said first bump is less than that between said first passive device and said second bump.
10. A chip package comprising:
a circuit substrate;
a first chip over said circuit substrate;
a first bump under said circuit substrate;
a second bump connecting said first chip and said circuit substrate, wherein said second bump has a height less than that of said first bump;
a first passive device over said circuit substrate;
a second passive device under said circuit substrate.
11. The chip package of claim 10 further comprising a second chip over said circuit substrate.
12. The chip package of claim 10 , wherein said second passive device is under said first chip.
13. The chip package of claim 10 , wherein said first bump comprises solder.
14. The chip package of claim 10 , wherein said first passive device comprises a capacitor.
15. The chip package of claim 10 , wherein said first passive device comprises a capacitor and said second passive device comprises a capacitor.
16. The chip package of claim 10 , wherein said circuit substrate comprises a printed circuit board.
17. A chip package comprising:
a circuit substrate comprising a via connector extending in a vertical direction and a ground plane spreading in a horizontal level and contacting said via connector;
a first chip joined with said circuit substrate;
a second chip joined with said circuit substrate;
a capacitor connected to said circuit substrate; and
a connecting portion over said via connector and over said circuit substrate, wherein said connecting portion connects said via connector and said capacitor.
18. The chip package of claim 17 , wherein said circuit substrate further comprises a power plane connected to said capacitor.
19. A chip package comprising:
a circuit substrate comprising a via connector extending in a vertical direction and a ground plane spreading in a horizontal level and contacting said via connector;
a first bump under said circuit substrate, wherein said first bump comprises solder;
a first chip over said circuit substrate;
a capacitor over said circuit substrate; and
a connecting portion over said via connector, wherein said connecting portion connects said via connector and said capacitor.
20. The chip package of claim 19 , wherein said circuit substrate further comprises a power plane connected to said capacitor.
21. A chip package comprising:
a circuit substrate consisting of multiple circuit layers arranged in parallel, the topmost one of said multiple circuit layers comprising a trace, a first contact and a second contact, said trace said first and second contacts, wherein said trace is at the same horizontal level as said first and second contacts are;
a first chip over said circuit substrate;
a first bump between said first chip and said first contact, wherein said first bump is in contact with said first contact; and
a passive device over said circuit substrate, wherein said passive device is connected to said second contact.
22. The chip package of claim 21 further comprising a second chip over said circuit substrate, wherein the topmost one of said multiple circuit layers further comprises a third contact connected to said first and second contacts and to said second chip.
23. The chip package of claim 21 , wherein said multiple circuit layers comprise a power plane connected to said trace.
24. The chip package of claim 21 , wherein said multiple circuit layers comprise a ground plane connected to said trace.
25. The chip package of claim 21 further comprising a first bump comprising solder.
26. A chip package comprising:
a circuit substrate;
a first chip over said circuit substrate;
a second chip over said circuit substrate; and
a passive device over said circuit substrate, wherein said passive device is between said first and second chips, and wherein said circuit substrate comprises a portion connecting said first and second chips and said passive device.
27. The chip package of claim 26 further comprising a bump between said first chip and said circuit substrate.
28. The chip package of claim 27 , wherein said bump comprises solder.
29. The chip package of claim 26 further comprising a bump under said circuit substrate.
30. The chip package of claim 4 , wherein said second passive device comprises a capacitor.
31. The chip package of claim 10 , wherein said second bump comprises solder.
32. The chip package of claim 17 further comprising a bump between said first chip and said circuit substrate.
33. The chip package of claim 32 , wherein said bump comprises solder.
34. The chip package of claim 17 further comprising a first bump between said first chip and said circuit substrate, and a second bump between said second chip and said circuit substrate.
35. The chip package of claim 34 , wherein said first and second bumps comprise solder.
36. The chip package of claim 17 , wherein said first and second chips are over said circuit substrate, and said capacitor is under said circuit substrate.
37. The chip package of claim 17 , wherein said first and second chips and said capacitor are over said circuit substrate.
38. The chip package of claim 17 further comprising a first bump joined with said circuit substrate, and a second bump joined with said circuit substrate, wherein said capacitor is between said first and second bumps.
39. The chip package of claim 38 , wherein said first and second bumps comprise solder.
40. The chip package of claim 19 further comprising a second bump between said first chip and said circuit substrate.
41. The chip package of claim 40 , wherein said second bump comprises solder.
42. The chip package of claim 40 , wherein said first bump has a height greater than that of said second bump.
43. The chip package of claim 19 further comprising a second chip over said circuit substrate.
44. The chip package of claim 43 further comprising a second bump between said second chip and said circuit substrate.
45. The chip package of claim 44 , wherein said second bump comprises solder.
46. The chip package of claim 22 further comprising a second bump between said second chip and said third contact.
47. The chip package of claim 46 , wherein said second bump comprises solder.
48. The chip package of claim 21 further comprising a second bump under said circuit substrate.
49. The chip package of claim 48 , wherein said second bump comprises solder.
50. The chip package of claim 21 , wherein said passive device comprises a capacitor.
51. The chip package of claim 22 , wherein said passive device is between said first and second chips.
52. The chip package of claim 29 , wherein said bump comprises solder.
53. The chip package of claim 26 further comprising a first bump between said first chip and said circuit substrate, and a second bump between said second chip and said circuit substrate.
54. The chip package of claim 26 , wherein said passive device comprises a capacitor.
55. The chip package of claim 26 , wherein said circuit substrate comprises a power plane connected to said portion.
56. The chip package of claim 26 , wherein said circuit substrate comprises a ground plane to said portion.