Patent Assignment
Reel/Frame 017566/0028
Assignment of Assignor's Interest
Recorded: 2006-05-03
Received: 2006-05-03
Pages: 7
Assignor
MEGIC CORPORATION
Executed: 2006-04-28
Assignee
MEGICA CORPORATION
NO. 47, PARK 2ND RD. SCIENCE-BASED INDUSTRIAL PARK, ROOM 301/302, HSINCHU, TWX, TAIWAN
Covered Properties
(51)
Structure and manufacturing method of a chip scale package
Application:
11/389,717 →
Method of Metal Sputtering for Integrated Circuit Metal Routing
Application:
11/364,375 →
Electric Power Connection for Electrically Assisted Turbocharger
Application:
10/567,509 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
11/273,085 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
11/273,447 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
11/273,105 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
11/273,071 →
Post passivation metal scheme for high-performance integrated circuit devices
Application:
11/203,646 →
Semiconductor Chip with Redistribution Metal Layer
Application:
11/183,300 →
Multiple Selectable Function Integrated Circuit Module
Application:
11/181,175 →
Structure of Gold Bumps and Gold Conductors on One Ic Die and Methods of Manufacturing the Structures
Application:
11/178,541 →
Low Fabrication Cost, High Performance, High Reliability Chip Scale Package
Application:
11/136,650 →
Low Fabrication Cost, High Performance, High Reliability Chip Scale Package
Application:
11/120,234 →
High Performance System-on-Chip Using Post Passivation Process
Application:
11/092,379 →
Very Thick Metal Interconnection Scheme in Ic Chips
Application:
11/087,955 →
High Performance System-on-Chip Discrete Components Using Post Passivation Process
Application:
11/062,276 →
High Performance System-on-Chip Discrete Components Using Post Passivation Process
Application:
11/062,277 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
11/017,145 →
Post Passivation Interconnection Structures
Application:
11/017,169 →
Top Layers of Metal for Integrated Circuits
Application:
11/017,168 →
Chip Package with Die and Substrate
Application:
10/996,537 →
Chip Package with Die and Substrate
Application:
10/996,535 →
Post Passivation Interconnection Process and Structures
Application:
10/970,871 →
Reliable Metal Bumps on Top of I/O Pads After Removal of Test Probe Marks
Application:
10/962,964 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
10/962,963 →
Method of Metal Sputtering for Integrated Circuit Metal Routing
Application:
10/954,781 →
Top Layers of Metal for Integrated Circuits
Application:
10/948,020 →
Post Passivation Interconnection Process and Structures
Application:
10/937,543 →
Low Fabrication Cost, Fine Pitch and High Reliability Solder Bump
Application:
10/935,451 →
Method for Fabricating Thermal Compliant Semiconductor Chip Wiring Structure for Chip Scale Packaging
Application:
10/925,302 →
Method for Making High-Performance Rf Integrated Circuits
Application:
10/856,377 →
Wafer Level Processing Method and Structure to Manufacture Two Kinds of Interconnects, Gold and Solder, on One Wafer
Application:
10/855,086 →
Prosthetic Attachment Locking Device with Dual Locking Mechanism
Application:
10/810,519 →
High Performance Ic Chip Having Discrete Decoupling Capacitors Attached to Its Ic Surface
Application:
10/802,566 →
Wirebond Pad for Semiconductor Chip or Wafer
Application:
10/796,427 →
Method for improving semiconductor wafer test accuracy
Application:
10/786,807 →
Post Passivation Structure for Semiconductor Chip or Wafer
Application:
10/783,195 →
Thin film semiconductor package and method of fabrication
Application:
10/690,350 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
10/685,872 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
10/653,628 →
Structure of High Performance Combo Chip and Processing Method
Application:
10/614,928 →
High Performance System-on-Chip Passive Device Using Post Passivation Process
Application:
10/445,559 →
High Performance System-on-Chip Inductor Using Post Passivation Process
Application:
10/445,558 →
Multiple Chips Bonded to Packaging Structure with Low Noise and Multiple Selectable Functions
Application:
10/437,333 →
Method of Wire Bonding Over Active Area of a Semiconductor Circuit
Application:
10/434,142 →
High Performance Sub-System Design and Assembly
Application:
10/420,596 →
Electronic Device and Chip Package
Application:
10/420,595 →
Multiple Chips Bonded to Packaging Structure with Low Noise and Multiple Selectable Functions
Application:
10/371,505 →
Post Passivation Method for Semiconductor Chip or Wafer
Application:
10/154,662 →
Structure and manufacturing method of a chip scale package
Application:
09/837,007 →
Structure and Manufactruing Method of Chip Scale Package
Application:
09/821,546 →