Post passivation interconnection schemes on top of the IC chips
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A method for fabricating a circuit component comprising:
providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a passivation layer over said metallization structure, wherein said metallization structure is formed by a damascene process; and
forming a passive device over said passivation layer, wherein said forming said passive device comprises:
depositing a first metal layer over said passivation layer,
after said depositing said first metal layer, forming a patterned photoresist layer,
after said forming said patterned photoresist layer, electroplating a second metal layer,
after said electroplating said second metal layer, removing said patterned photoresist layer, and
after said removing said patterned photoresist layer, etching said first metal layer.
2. The method of claim 1 , wherein said damascene process comprises electroplating and CMP.
3. The method of claim 1 , wherein said passive device comprises an inductor.
4. The method of claim 1 , wherein said passive device comprises a layer of gold.
5. The method of claim 1 further comprising providing a transistor in said semiconductor substrate.
6. The method of claim 1 , wherein said forming said patterned photoresist layer comprising coating.
7. The method of claim 1 , wherein said passivation layer is formed by a process comprising:
depositing an oxide layer, and
after said depositing said oxide layer, depositing a nitride layer.
8. The method of claim 1 , wherein said depositing said first metal layer comprises sputtering.
9. The method of claim 1 , wherein said semiconductor substrate comprises a silicon substrate.
10. The method of claim 1 , wherein said passivation layer comprises a topmost nitride layer of said circuit component.
11. A method for fabricating a circuit component comprising:
providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a passivation layer over said metallization structure, wherein said metallization structure is formed by a damascene process; and
forming an inductor over said passivation layer, wherein said forming said inductor comprises:
depositing a first metal layer over said passivation layer,
after said depositing said first metal layer, forming a patterned photoresist layer,
after said forming said patterned photoresist layer, electroplating a second metal layer,
after said electroplating said second metal layer, removing said patterned photoresist layer, and
after said removing said patterned photoresist layer, etching said first metal layer.
12. The method of claim 11 , wherein said damascene process comprises electroplating and CMP.
13. The method of claim 11 further comprising providing a transistor in said semiconductor substrate.
14. The method of claim 11 , wherein said inductor comprises a layer of gold.
15. The method of claim 11 , wherein said forming said patterned photoresist layer comprises coating.
16. The method of claim 11 , wherein said passivation layer is formed by a process comprising:
depositing an oxide layer, and
after said depositing said oxide layer, depositing a nitride layer.
17. The method of claim 11 , wherein said depositing said first metal layer comprises sputtering.
18. The method of claim 11 , wherein said semiconductor substrate comprises a silicon substrate.
19. The method of claim 11 , wherein said passivation layer comprises a topmost nitride layer of said circuit component.