Structure of high performance combo chip and processing method
View Patent ↗A new method and package for the mounting of semiconductor devices. A silicon substrate serves as the device supporting medium, active semiconductor devices have been created in or on the surface of the silicon substrate. A solder plate is created over the surface of the substrate that aligns with the metal points of contact in the surface of the substrate. Semiconductor devices that have been provided with solder bumps or pin-grid arrays are connected to the solder plate. Underfill is applied to the connected semiconductor devices, the devices are covered with a layer of dielectric that is planarized. Inter-device vias are created in the layer of dielectric down to the surface of the substrate, re-routing interconnect lines are formed on the surface of the dielectric. Contact balls are connected to the re-routing lines after which the semiconductor devices that have been mounted above the silicon substrate are separated by die sawing. At this time, the separated semiconductor devices have two levels of ball interconnects, this can be further extended to for instance three levels of balls interconnect be connecting the second level of ball interconnect to a first surface of a Printed Circuit Board (PCB) while additional contact balls are connected to a second surface of this PCB.
1. A chip package comprising:
a first semiconductor chip;
a second semiconductor chip joined with a top surface of said first semiconductor chip;
a first insulating layer covering a sidewall of said second semiconductor chip and said top surface of said first semiconductor chip, wherein said first insulating layer comprises a top surface substantially parallel to said top surface of said first semiconductor chip; and
a metal layer over said top surface of said first insulating layer.
2. The chip package of claim 1 further comprising a bump between said first and second semiconductor chips.
3. The chip package of claim 2 further comprising a second insulating layer between said first and second semiconductor chips and enclosing said bump.
4. The chip package of claim 1 further comprising a via through said first insulating layer and connecting said first semiconductor chip and said metal layer.
5. The chip package of claim 1 , wherein said top surface of said first insulating layer has a first region and a second region, said first region being over said second semiconductor chip, said second region being over said first semiconductor chip but not over said second semiconductor chip, wherein said first and second regions are substantially coplanar.
6. The chip package of claim 5 , wherein said metal layer is on said first and second regions.
7. The chip package of claim 1 further comprising a first bump over said metal layer.
8. The chip package of claim 1 , wherein said second semiconductor chip comprises a top surface and a bottom surface facing said top surface of said first semiconductor chip, said first insulating layer being further over said top surface of said second semiconductor chip.
9. The chip package of claim 7 further comprising a substrate and a second bump connected to a bottom surface of said substrate, wherein said first bump is connected to a top surface of said substrate.
10. The chip package of claim 9 further comprising an underfill between said substrate and said first insulating layer and enclosing said first bump.
11. The chip package of claim 1 , wherein said metal layer is on said top surface of said first insulating layer.
12. The chip package of claim 11 further comprising a bump on said metal layer.