IP Library Granted Patent US 7,372,162
Granted Patent B2
US 7,372,162 · App. 11/181,175 · Granted May 13, 2008

Multiple selectable function integrated circuit module

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Quick Facts
Patent No.
US 7,372,162
App. No.
11/181,175
Granted
May 13, 2008
Kind
B2
Abstract

An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module. The second level module substrate has connector pins to provide physical and electrical connections between the external circuitry and the wiring connections on the second level substrate.

Claims (26)

1. A circuit component comprising:

a substrate;

a solder mask on said substrate, wherein an opening in said solder mask exposes a pad of said substrate;

a die over said substrate in a flip-chip assembly, wherein said die comprises a first functional circuit and a second functional circuit;

a first solder bump between said die and said substrate, wherein said first solder bump connects said first functional circuit to said pad through said opening; and

a second solder bump between said die and said substrate, wherein said second solder bump is connected to said second functional circuit, and wherein said second solder bump is not connected to any pad of said substrate.

2. The circuit component of claim 1 , wherein said die comprises a DRAM.

3. The circuit component of claim 1 , wherein said first functional circuit implements a DRAM array address function.

4. The circuit component of claim 1 , wherein said first functional circuit implements a SRAM array address function.

5. The circuit component of claim 1 , wherein said first functional circuit implements a non-volatile memory array address function.

6. The circuit component of claim 1 , wherein said second functional circuit implements a function to select one from multiple types of data width.

7. The circuit component of claim 6 , wherein said multiple types of data width comprise by-sixteen data width.

8. The circuit component of claim 6 , wherein said multiple types of data width comprise by-eight data width.

9. A circuit component comprising:

a substrate comprising a metal interconnection;

a solder mask on said substrate, wherein an opening in said solder mask exposes a pad of said metal interconnection;

a die over said substrate in a flip-chip assembly, wherein said die comprises a first functional circuit and a second functional circuit;

a first solder bump between said die and said substrate, wherein said first solder bump connects said first functional circuit to said pad through said opening, and

wherein said metal interconnection connects said first functional circuit to an external circuit of said die and said substrate; and

a second solder bump between said die and said substrate, wherein said second solder bump is connected to said second functional circuit, and wherein said second solder bump is not connected to any external circuit of said die and said substrate.

10. The circuit component of claim 9 , wherein said die comprises a DRAM.

11. The circuit component of claim 9 , wherein said first functional circuit implements a DRAM array address function.

12. The circuit component of claim 9 , wherein said first functional circuit implements a SRAM array address function.

13. The circuit component of claim 9 , wherein said first functional circuit implements a non-volatile memory array address function.

14. The circuit component of claim 13 , wherein said second functional circuit implements a function to select one from multiple types of data width.

15. The circuit component of claim 14 , wherein said multiple types of data width comprise by-sixteen data width.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2014
From: MEGIT ACQUISITION CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 033303/0124 →
MERGER Recorded Sep 25, 2013
From: MEGICA CORPORATION
To: MEGIT ACQUISITION CORP.
Reel/Frame 031283/0198 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2013
From: LIN, MOU-SHIUNG
To: MEGIC CORPORATION
Reel/Frame 030769/0642 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2006
From: MEGIC CORPORATION
To: MEGICA CORPORATION
Reel/Frame 017566/0028 →