Low fabrication cost, high performance, high reliability chip scale package
View Patent ↗The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
1. An integrated circuit device comprising:
a silicon substrate;
a contact pad over said silicon substrate;
a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said contact pad;
a metal trace over said passivation layer and over said contact pad; and
a bump on said metal trace, wherein said bump comprises a copper layer directly on said metal trace, a nickel layer over said copper layer, and a solder layer directly on a top surface of said nickel layer, wherein said copper layer has a first transverse dimension smaller than a second transverse dimension of said nickel layer and has a thickness greater than said first transverse dimension, wherein said copper layer has a sidewall recessed from that of said nickel layer, and wherein said nickel layer has a first portion over said copper layer and a second portion overhanging said copper layer.
2. The integrated circuit device of claim 1 further comprising a polymer layer between said passivation layer and said metal trace.
3. The integrated circuit device of claim 2 , wherein said polymer layer comprises polyimide.
4. The integrated circuit device of claim 2 , wherein said polymer layer comprises bisbenzocyclobutene (BCB).
5. The integrated circuit device of claim 2 , wherein said polymer layer comprises parylene.
6. The integrated circuit device of claim 1 , wherein said copper layer has a thickness between 10 and 100 micrometers.
7. The integrated circuit device of claim 1 , wherein said nickel layer has a thickness between 1 and 10 micrometers.
8. The integrated circuit device of claim 1 , wherein said metal trace has a region exposed to the outside.
9. The integrated circuit device of claim 1 , wherein said solder layer has a thickness of between 10 μm and 100 μm.
10. The integrated circuit device of claim 1 , wherein the position of said bump from a top view is different from that of said contact pad.
11. The integrated circuit device of claim 1 , wherein said contact pad comprises copper.
12. The integrated circuit device of claim 1 , wherein said metal trace comprises a titanium-containing layer and a copper layer over said titanium-containing layer.
13. The integrated circuit device of claim 12 , wherein said titanium-containing layer further comprises tungsten.
14. The integrated circuit device of claim 1 , wherein said contact pad comprises aluminum.
15. The integrated circuit device of claim 1 , wherein said nickel layer is directly on said copper layer.
16. An integrated circuit device comprising:
a silicon substrate;
a first pad over said silicon substrate;
a passivation layer over said silicon substrate, an opening in said passivation layer exposing said first pad;
a metal trace over said passivation layer and over said first pad, said metal trace comprising a second pad connected to said first pad through said opening, wherein the positions of said first and second pads from a top perspective view are different; and
a bump on said second pad, wherein said bump comprises a metal layer having a thickness between 10 and 100 micrometers over said second pad, a nickel layer over said metal layer, and a solder layer having a thickness between 10 and 100 micrometers over said nickel layer, wherein said metal layer has a transverse dimension smaller than that of said nickel layer and smaller than said thickness of said metal layer, wherein said metal layer has a sidewall recessed from that of said nickel layer, and wherein said nickel layer has a first portion over said metal layer and a second portion overhanging said metal layer.
17. The integrated circuit device of claim 16 , wherein said nickel layer has a thickness between 1 and 10 micrometers.
18. The integrated circuit device of claim 16 further comprising a polymer layer between said metal trace and said passivation layer.
19. The integrated circuit device of claim 16 , wherein said layer comprises a copper layer with a thickness between 10 and 100 micrometers on said second pad.
20. The integrated circuit device of claim 16 , wherein said solder layer is electroplated.
21. An integrated circuit device comprising:
a silicon substrate;
a contact pad over said silicon substrate;
a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said contact pad;
a metal trace over said passivation layer and over said contact pad; and
a bump on said metal trace, wherein said bump comprises a metal layer having a thickness between 10 and 100 micrometers over said metal trace, a nickel layer over said metal layer, and a solder layer directly on a top surface of said nickel layer, wherein said metal layer has a transverse dimension smaller than that of said nickel layer and smaller that said thickness of said metal layer, wherein said metal layer has a sidewall recessed from that of said nickel layer, and wherein said nickel layer comprises a first portion over said metal layer and a second portion overhanging said metal layer.
22. The integrated circuit device of claim 21 , wherein said metal layer comprises a copper layer having a thickness between 10 and 100 micrometers on said metal trace.
23. The integrated circuit device of claim 21 , wherein said nickel layer has a thickness between 1 and 10 micrometers.
24. The integrated circuit device of claim 21 , wherein said solder layer has a thickness between 10 μm and 100 μm.
25. The integrated circuit device of claim 21 , wherein said solder layer is electroplated.
26. The integrated circuit device of claim 22 , wherein said nickel layer is directly on said copper layer.