Post passivation structure for semiconductor chip or wafer
View Patent ↗The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.
1. A semiconductor chip connected to a wirebond interconnect, comprising:
a silicon substrate;
a transistor in or on said silicon substrate;
a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a first contact pad over said silicon substrate, wherein said first contact pad has a top surface with a first region and a second region, wherein said second region surrounds said first region;
a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein said passivation layer has a thickness greater than that of said dielectric layer, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a size between 0.1 and 50 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 50 μm, greater than that of said dielectric layer and greater than that of said passivation layer;
a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises an electroplated gold layer with a thickness between 2 and 100 μm, wherein said second contact pad is connected to said first contact pad through said first and second openings, and wherein the positions of said first and second contact pads from a top perspective view are different; and
a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.
2. The semiconductor chip of claim 1 , wherein said second contact pad further comprises a titanium-containing layer under said electroplated gold layer.
3. The semiconductor chip of claim 2 , wherein said titanium-containing layer comprises tungsten.
4. The semiconductor chip of claim 2 , wherein said titanium-containing layer comprises nitrogen.
5. The semiconductor chip of claim 1 , wherein said polymer layer comprises polyimide.
6. A semiconductor chip connected to a wirebond interconnect, comprising:
a silicon substrate;
a transistor in or on said silicon substrate;
a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a first contact pad over said silicon substrate;
a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer has a thickness greater than that of said dielectric layer, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a polymer layer on said passivation layer, wherein an opening in said polymer layer is over said first contact pad and exposes said first contact pad, and wherein said polymer layer has a thickness between 2 and 50 μm, greater than that of said dielectric layer and greater than that of said passivation layer;
a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises an electroplated gold layer with a thickness between 2 and 100 μm, wherein said second contact pad is connected to said first contact pad through said opening, and wherein the positions of said first and second contact pads from a top perspective view are different; and
a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.
7. A semiconductor chip connected to a wirebond interconnect, comprising:
a silicon substrate;
a transistor in or on said silicon substrate;
a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a first contact pad over said silicon substrate, wherein said first contact pad has a top surface with a first region and a second region, wherein said second region surrounds said first region;
a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein said passivation layer has a thickness greater than that of said dielectric layer, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a size between 0.1 and 50 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 50 μm, greater than that of said dielectric layer and greater than that of said passivation layer;
a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises a titanium-containing layer with a thickness between 0.01 and 3 μm, a seed layer with a thickness between 0.05 and 3 μm over said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 μm on said seed layer, wherein said second contact pad is connected to said first contact pad through said first and second openings, and wherein the positions of said first and second contact pads from a top perspective view are different; and
a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.
8. The semiconductor chip of claim 2 , wherein said titanium-containing layer has a thickness between 0.01 and 3 μm.
9. The semiconductor chip of claim 2 , wherein said second contact pad further comprises a seed layer between said titanium-containing layer and said electroplated gold layer, wherein said seed layer has a thickness between 0.05 and 3 μm.
10. The semiconductor chip of claim 6 , wherein said second contact pad further comprises a titanium-containing layer under said electroplated gold layer.
11. The semiconductor chip of claim 10 , wherein said titanium-containing layer has a thickness between 0.01 and 3 μm.
12. The semiconductor chip of claim 10 , wherein said second contact pad further comprises a seed layer between said titanium-containing layer and said electroplated gold layer, wherein said seed layer has a thickness between 0.05 and 3 μm.
13. The semiconductor chip of claim 7 , wherein said polymer layer comprises polyimide.
14. The semiconductor chip of claim 6 , wherein said polymer layer comprises polyimide.