Low fabrication cost, high performance, high reliability chip scale package
View Patent ↗The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
1. A process for fabricating a circuit component, comprising:
providing a silicon substrate, a contact pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said contact pad;
depositing a first metal layer over said passivation layer and over said contact pad;
forming a first pattern-defining layer over said first metal layer, wherein an opening in said first pattern-defining layer exposes said first metal layer;
depositing a second metal layer over said first metal layer exposed by said opening in said first pattern-defining layer;
removing said first pattern-defining layer;
forming a second pattern-defining layer over said second metal layer, wherein an opening in said second pattern-defining layer exposes said second metal layer;
depositing a copper layer over said second metal layer exposed by said opening in said second pattern-defining layer;
depositing a nickel layer over said copper layer in said opening in said second pattern-defining layer;
depositing a solder layer over said nickel layer in said opening in said second pattern-defining layer;
removing said second pattern-defining layer; and
removing said first metal layer not under said second metal layer and reducing a transverse dimension of said copper layer.
2. The process of claim 1 further comprising forming a polymer layer on said passivation layer, followed by said depositing said first metal layer further on said polymer layer.
3. The process of claim 1 , wherein said depositing said first metal layer comprises sputtering.
4. The process of claim 1 , wherein said depositing said copper layer comprises electroplating said copper layer with a thickness between 10 and 100 micrometers over said second metal layer exposed by said opening in said second pattern-defining layer.
5. The process of claim 1 , after said removing said first metal layer not under said second metal layer, further comprising reflowing said solder layer.
6. The process of claim 1 , wherein said depositing said nickel layer comprises electroplating said nickel layer with a thickness between 1 and 10 micrometers over said copper layer in said opening in said second pattern-defining layer.
7. The process of claim 1 , wherein said depositing said solder layer comprises electroplating.
8. The process of claim 1 , wherein said depositing said solder layer comprises electroplating said solder layer with a thickness between 10 and 100 micrometers over said nickel layer in said opening in said second pattern-defining layer.
9. The process of claim 1 , wherein said depositing said second metal layer comprises electroplating.
10. The process of claim 1 , wherein said depositing said first metal layer comprises sputtering a titanium-containing layer over said passivation layer and over said contact pad.
11. A process for fabricating a circuit component, comprising:
providing a silicon substrate, a first pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said first pad;
providing a metal trace over said passivation layer and over said first pad, wherein said metal trace comprises a second pad connected to said first pad through said opening in said passivation layer, and wherein the position of said second pad from a top view is different from that of said first pad;
forming a pattern-defining layer on said metal trace, wherein an opening in said pattern-defining layer exposes said second pad;
depositing a copper layer over said second pad exposed by said opening in said pattern-defining layer;
depositing a nickel layer over said copper layer in said opening in said pattern-defining layer;
depositing a solder layer over said nickel layer in said opening in said pattern-defining layer;
removing said pattern-defining layer; and
reducing a transverse dimension of said copper layer.
12. The process of claim 11 further comprising providing a polymer layer between said metal trace and said passivation layer.
13. The process of claim 11 , after said removing said pattern-defining layer, further comprising reflowing said solder layer.
14. The process of claim 11 , wherein said depositing said copper layer comprises electroplating said copper layer with a thickness between 10 and 100 micrometers over said second pad exposed by said opening in said pattern-defining layer.
15. The process of claim 11 , wherein said depositing said nickel layer comprises electroplating a nickel layer with a thickness between 1 and 10 micrometers over said copper layer in said opening in said pattern-defining layer.
16. The process of claim 11 , wherein said metal trace is formed by a process comprising electroplating.
17. The process of claim 11 , wherein said depositing said solder layer comprises electroplating.
18. The process of claim 11 , wherein said depositing said solder layer comprises electroplating said solder layer with a thickness between 10 and 100 micrometers over said nickel layer in said opening in said pattern-defining layer.
19. The process of claim 12 , wherein said polymer layer comprises polyimide.
20. The process of claim 11 , wherein said first pad comprises copper.
21. A process for fabricating a circuit component, comprising:
providing a silicon substrate, a copper pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said copper pad;
depositing a first metal layer over said passivation layer and over said copper pad;
forming a first pattern-defining layer over said first metal layer, wherein an opening in said first pattern-defining layer exposes said first metal layer;
depositing a second metal layer over said first metal layer exposed by said opening in said first pattern-defining layer;
removing said first pattern-defining layer;
forming a second pattern-defining layer over said second metal layer, wherein an opening in said second pattern-defining layer exposes said second metal layer;
depositing a copper layer with a thickness between 10 and 100 micrometers over said second metal layer exposed by said opening in said second pattern-defining layer;
depositing a nickel layer over said copper layer in said opening in said second pattern-defining layer;
depositing a solder layer over said nickel layer in said opening in said second pattern-defining layer;
removing said second pattern-defining layer; and
removing said first metal layer not under said second metal layer and reducing a transverse dimension of said copper layer.
22. The process of claim 21 , wherein said depositing said second metal layer comprises electroplating.
23. The process of claim 21 , wherein said depositing said nickel layer comprises electroplating said nickel layer with a thickness between 1 and 10 micrometers over said copper layer in said opening in said second pattern-defining layer.
24. The process of claim 21 , wherein said depositing said solder layer comprises electroplating said solder layer with a thickness between 10 and 100 micrometers over said nickel layer in said opening in said second pattern-defining layer.
25. The process of claim 21 further comprising providing a polymer layer on said passivation layer, followed by said depositing said first metal layer further on said polymer layer.