Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
View Patent ↗A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.
1. A method for fabricating a circuitry component comprising:
providing a silicon substrate and a passivation layer over said silicon substrate;
forming a sacrificial layer over said passivation layer;
depositing a first metal layer comprising a first portion over said sacrificial layer and a second portion over said passivation layer but not over said sacrificial layer;
forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first and second portions;
depositing a second metal layer over said first and second portions exposed by said first opening;
removing said first pattern-defining layer;
removing said first metal layer not under said second metal layer; and
removing said sacrificial layer.
2. The method of claim 1 , wherein said depositing said second metal layer comprises electroplating.
3. The method of claim 1 , wherein said sacrificial layer is patterned underlying a location where a bump is to be formed.
4. The method of claim 1 , wherein said sacrificial layer comprises polymer.
5. The method of claim 1 further comprising depositing a bump over said second metal layer over a void formed by said removing said sacrificial layer.
6. The method of claim 1 further comprising placing a solder ball over said second metal layer over a void formed by said removing said sacrificial layer.
7. The method of claim 1 , wherein said forming said sacrificial layer comprises spin-coating.
8. The method of claim 1 , wherein said forming said sacrificial layer comprises laminating.
9. The method of claim 1 , wherein said forming said sacrificial layer comprises printing.
10. The method of claim 1 , further comprising:
forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer;
depositing a third metal layer over said second metal layer exposed by said second opening; and
removing said second pattern-defining layer.
11. The method of claim 10 , wherein said depositing said third metal layer comprises depositing gold over said second metal layer exposed by said second opening.
12. The method of claim 10 , wherein said depositing said third metal layer comprises depositing tin over said second metal layer exposed by said second opening.
13. The method of claim 10 , wherein said depositing said third metal layer comprises electroplating.
14. The method of claim 1 , wherein said depositing said second metal layer further comprises depositing copper over said first and second portions exposed by said first opening.
15. The method of claim 1 , wherein said depositing said second metal layer further comprises depositing gold over said first and second portions exposed by said first opening.
16. A method for fabricating a circuitry component comprising:
providing a silicon substrate and a passivation layer over said silicon substrate;
forming an insulating layer over said passivation layer;
depositing a first metal layer over said insulating layer;
forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer;
depositing a second metal layer over said first metal layer exposed by said first opening;
removing said first pattern-defining layer;
removing said first metal layer not under said second metal layer; and
after said depositing said first metal layer, removing said insulating layer.
17. The method of claim 16 , wherein said depositing said second metal layer comprises electroplating.
18. The method of claim 16 , wherein said insulating layer is patterned underlying a location where a bump is to be formed.
19. The method of claim 16 , wherein said insulating layer comprises polymer.
20. The method of claim 16 further comprising depositing a bump over said second metal layer over a void formed by said removing said insulating layer.
21. The method of claim 16 further comprising placing a solder ball over said second metal layer over a void formed by said removing said insulating layer.
22. The method of claim 16 , wherein said forming said insulating layer comprises spin-coating.
23. The method of claim 16 , wherein said forming said insulating layer comprises printing.
24. The method of claim 16 , further comprising:
forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer;
depositing a third metal layer over said second metal layer exposed by said second opening; and
removing said second pattern-defining layer.
25. The method of claim 24 , wherein said depositing said third metal layer comprises depositing gold over said second metal layer exposed by said second opening.
26. The method of claim 24 , wherein said depositing said third metal layer comprises depositing tin over said second metal layer exposed by said second opening.
27. The method of claim 24 , wherein said depositing said third metal layer comprises electroplating.
28. The method of claim 16 , wherein said depositing said second metal layer further comprises depositing copper over said first metal layer exposed by said first opening.
29. The method of claim 16 , wherein said depositing said second metal layer further comprises depositing gold over said first metal layer exposed by said first opening.
30. A method for fabricating a circuitry component comprising:
providing a silicon substrate and a passivation layer over said silicon substrate;
forming an insulating layer over said passivation layer;
electroplating a metal layer over said insulating layer; and
after said electroplating said metal layer, removing said insulating layer.
31. The method of claim 30 , wherein said insulating layer is patterned underlying a location where a bump is to be formed.
32. The method of claim 30 , wherein said insulating layer comprises polymer.
33. The method of claim 30 further comprising depositing a bump over said metal layer over a void formed by said removing said insulating layer under said metal layer.
34. The method of claim 30 further comprising placing a solder ball over said metal layer over a void formed by said removing said insulating layer under said metal layer.
35. The method of claim 30 , wherein said forming said insulating layer comprises spin-coating.
36. The method of claim 30 , wherein said forming said insulating layer comprises laminating.
37. The method of claim 30 , wherein said forming said insulating layer comprises printing.
38. The method of claim 30 , wherein said metal layer comprises gold.
39. The method of claim 30 , wherein said metal layer comprises copper.
40. The method of claim 30 , wherein said metal layer comprises nickel.
41. The method of claim 1 , wherein said depositing said second metal layer further comprises depositing nickel over said first and second portions exposed by said first opening.
42. The method of claim 16 , wherein said depositing said second metal layer further comprises depositing nickel over said first metal layer exposed by said first opening.