Post passivation interconnection schemes on top of the IC chips
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A circuitry component comprising:
a semiconductor substrate;
an internal circuit in or on said semiconductor substrate;
a first intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit;
a second intra-chip driver or receiver in or on said semiconductor substrate;
a first metallization structure over said semiconductor substrate;
a passivation layer over said first metallization structure; and
a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said first intra-chip driver or receiver and said second intra-chip driver or receiver.
2. The circuitry component of claim 1 , wherein said passivation layer comprises a topmost nitride layer of said circuitry component.
3. The circuitry component of claim 1 , wherein said passivation layer comprises a topmost oxide layer of said circuitry component.
4. The circuitry component of claim 1 , wherein said passivation layer comprises a topmost CVD insulating layer of said circuitry component.
5. The circuitry electronic component of claim 1 , wherein said second metallization structure is used to transmit address signals.
6. The circuitry component of claim 1 , wherein said second metallization structure is used to transmit data signals.
7. The circuitry component of claim 1 , wherein said second metallization structure is used to transmit logic signals.
8. The circuitry component of claim 1 , wherein said second metallization structure is used to transmit analog signals.
9. The circuitry component of claim 1 , wherein said second metallization structure is used to transmit clock signals.
10. The circuitry component of claim 1 , wherein said second metallization is used to transmit a power voltage.
11. The circuitry component of claim 1 , wherein said second metallization structure is used to transmit a ground voltage.
12. The circuitry component of claim 1 further comprising an off-chip driver, receiver or I/O circuit in or on said semiconductor substrate, and an external connection connected to said off-chip driver, receiver or I/O circuit, wherein said first and second metallization structures connect said off-chip driver, receiver or I/O circuit, said first intra-chip driver or receiver, and said second intra-chip driver or receiver.
13. The circuitry component of claim 12 further comprising an ESD circuit in or on said semiconductor substrate and connected to said external connection.
14. The circuitry component of claim 1 is a chip.
15. The circuitry component of claim 1 is a wafer.
16. The circuitry component of claim 1 , wherein said second metallization structure is used to transmit a power voltage output from a voltage regulator.
17. An circuitry component comprising:
a semiconductor substrate;
an internal circuit in or on said semiconductor substrate;
an intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit;
an off-chip driver, receiver or I/O circuit in or on said semiconductor substrate;
a first metallization structure over said semiconductor substrate;
an external connection connected to said off-chip driver, receiver or I/O circuit;
a passivation layer over said first metallization structure; and
a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said intra-chip driver or receiver and said off-chip driver, receiver or I/O circuit.
18. The circuitry component of claim 17 , wherein said passivation layer comprises a topmost nitride layer of said circuitry component.
19. The circuitry component of claim 17 , wherein said passivation layer comprises a topmost oxide layer of said circuitry component.
20. The circuitry component of claim 17 , wherein said passivation layer comprises a topmost CVD insulating layer of said circuitry component.
21. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit address signals.
22. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit data signals.
23. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit logic signals.
24. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit analog signals.
25. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit clock signals.
26. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit a power voltage.
27. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit a ground voltage.
28. The circuitry component of claim 17 further comprising an ESD circuit in or on said semiconductor substrate and connected to said external connection.
29. The circuitry component of claim 17 is a chip.
30. The circuitry component of claim 17 is a wafer.
31. The circuitry component of claim 17 , wherein said second metallization structure is used to transmit a power voltage output from a voltage regulator.
32. A method of fabricating a circuit component, comprising:
providing a wafer comprising a semiconductor substrate, an internal circuit in or on said semiconductor substrate, a first intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit, a second intra-chip driver or receiver in or on said semiconductor substrate, a first metallization structure over said semiconductor substrate, and a passivation layer, over said first metallization structure; and
forming a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said first intra-chip driver or receiver and said second intra-chip driver or receiver.
33. The method of claim 32 , wherein said passivation layer comprises a nitride layer.
34. The method of claim 32 , wherein said passivation layer comprises an oxide layer.
35. The method of claim 32 , wherein said passivation layer comprises an insulating layer formed using a CVD process.
36. The method of claim 32 , wherein said forming said second metallization structure comprises electroplating.
37. The method of claim 32 , wherein said forming said second metallization structure comprises sputtering.
38. A method of fabricating a circuit component, comprising:
providing a wafer comprising a semiconductor substrate, an internal circuit in or on said semiconductor substrate, an intra-chip driver or receiver, in or on said semiconductor substrate and connected to said internal circuit, an off-chip driver, receiver or I/O circuit in or on said semiconductor substrate, a first metallization structure over said semiconductor substrate, an external connection connected to said off-chip driver, receiver or I/O circuit, and a passivation layer over said first metallization structure; and
forming a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said intra-chip driver or receiver and said off-chip driver, receiver or I/O circuit.
39. The method of claim 38 , wherein said passivation layer comprises a nitride layer.
40. The method of claim 38 , wherein said passivation layer comprises an oxide layer.
41. The method of claim 38 , wherein said passivation layer comprises an insulating layer formed using a CVD process.
42. The method of claim 38 , wherein said forming said second metallization structure comprises electroplating.
43. The method of claim 38 , wherein said forming said second metallization structure comprises sputtering.
44. The circuitry component of claim 1 , wherein said passivation layer comprises a nitride layer having a thickness of greater than 0.4 microns.
45. The circuitry component of claim 1 , wherein said internal circuit has no ESD circuit and no I/O circuit.
46. The circuitry component of claim 1 , wherein said first intra-chip driver or receiver is in series connected to said internal circuit.
47. The circuitry component of claim 13 , wherein said ESD circuit is in parallel connected to said off-chip driver, receiver or I/O circuit.
48. The circuitry component of claim 1 , wherein said second metallization structure comprises an interconnecting line having a thickness of greater than 1 micrometer.
49. The circuitry component of claim 17 , wherein said passivation layer comprises a nitride layer having a thickness of greater than 0.4 microns.
50. The circuitry component of claim 17 , wherein said internal circuit has no ESD circuit and no I/O circuit.
51. The circuitry component of claim 17 , wherein said intra-chip driver or receiver is in series connected to said internal circuit.
52. The circuitry component of claim 28 , wherein said ESD circuit is in parallel connected to said off-chip driver, receiver or I/O circuit.
53. The circuitry component of claim 17 , wherein said second metallization structure comprises an interconnecting line having a thickness of greater than 1 micrometer.
54. The method of claim 32 , wherein said passivation layer comprises a nitride layer having a thickness of greater than 0.4 microns.
55. The method of claim 32 , wherein said internal circuit has no ESD circuit and no I/O circuit.
56. The method of claim 38 , wherein said passivation layer comprises a nitride layer having a thickness of greater than 0.4 microns.
57. The method of claim 38 , wherein said internal circuit has no ESD circuit and no I/O circuit.