Chip package with die and substrate
View Patent ↗A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
1. A chip package comprising:
a glass substrate;
only one semiconductor die having a back surface joined with said glass substrate;
a first polymer layer over said glass substrate and at a horizontal outside of said only one semiconductor die;
a second polymer layer on a top surface of said only one semiconductor die, on said first polymer layer and over said horizontal outside, wherein said second polymer layer has a thickness between 5 and 100 micrometers;
a first patterned metal layer over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said first patterned metal layer is connected to said only one semiconductor die through an opening in said second polymer layer, and wherein said first patterned metal layer comprises sputtered copper and has a thickness between 1 and 150 micrometers;
a third polymer layer on said first patterned metal layer, over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said third polymer layer has a thickness between 1 and 150 micrometers;
a second patterned metal layer on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, and wherein said second patterned metal layer comprises an electroplated metal;
an insulating layer on said second patterned metal layer, on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein an opening in said insulating layer is over a pad of said second patterned metal layer and exposes said pad; and
a solder bump over said pad of said second patterned metal layer and directly over said horizontal outside, wherein said solder bump is connected to said second patterned metal layer through said opening in said insulating layer.
2. The chip package of claim 1 , wherein said first polymer layer comprises epoxy.
3. The chip package of claim 1 , wherein said second polymer layer comprises polyimide.
4. The chip package of claim 1 , wherein said second polymer layer comprises benzocyclobutene (BCB).
5. The chip package of claim 1 , wherein said first patterned metal layer comprises an inductor.
6. A chip package comprising:
a substrate;
only one semiconductor die having a back surface joined with said substrate;
a first polymer layer over said substrate and at a horizontal outside of said only one semiconductor die;
a second polymer layer on a top surface of said only one semiconductor die, on said first polymer layer and over said horizontal outside, wherein said second polymer layer has a thickness of between 5 and 100 micrometers;
a first patterned metal layer over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said first patterned metal layer is connected to said only one semiconductor die through an opening in said second polymer layer, and wherein said first patterned metal layer comprises sputtered copper and has a thickness between 1 and 150 micrometers;
a third polymer layer on said first patterned metal layer, over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said third polymer layer has a thickness between 1 and 150 micrometers;
a second patterned metal layer on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, and wherein said second patterned metal layer comprises an electroplated metal;
an insulating layer on said second patterned metal layer, on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein an opening in said insulating layer is over a pad of said second patterned metal layer and exposes said pad; and
a solder bump over said pad of said second patterned metal layer and directly over said horizontal outside, wherein said solder bump is connected to said second patterned metal layer through said opening in said insulating layer.
7. The chip package of claim 6 , wherein said first polymer layer comprises epoxy.
8. The chip package of claim 6 , wherein said second polymer layer comprises polyimide.
9. The chip package of claim 6 , wherein said second polymer layer comprises benzocyclobutene (BCB).
10. The chip package of claim 6 , wherein said first patterned metal layer comprises an inductor.
11. A chip package comprising:
a substrate;
a semiconductor die having a back surface joined with said substrate;
a first polymer layer on a top surface of said semiconductor die and over a horizontal outside of said semiconductor die, wherein said first polymer layer has a thickness between 5 and 100 micrometers; and
a first patterned metal layer on said first polymer layer, over said top surface of said semiconductor die and over said horizontal outside, wherein said first patterned metal layer is connected to said semiconductor die through an opening in said first polymer layer, wherein said first patterned metal layer comprises an electroplated metal and has a thickness between 1 and 150 micrometers, and wherein said first patterned metal layer comprises an inductor.
12. The chip package of claim 11 , wherein said substrate comprises glass.
13. The chip package of claim 11 further comprising a second polymer layer at said horizontal outside and between said substrate and said first polymer layer.
14. The chip package of claim 11 , wherein said first polymer layer comprises polyimide.
15. The chip package of claim 11 , wherein said first polymer layer comprises benzocyclobutene (BCB).
16. The chip package of claim 11 further comprising a solder bump over said horizontal outside, wherein said solder bump is connected to said first patterned metal layer.
17. The chip package of claim 11 further comprising a second polymer layer on said first patterned metal layer, on said first polymer layer, over said top surface of said semiconductor die and over said horizontal outside.
18. The chip package of claim 17 , further comprising a second patterned metal layer on said second polymer layer, over said top surface of said semiconductor die and over said horizontal outside, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said second polymer layer.
19. The chip package of claim 11 further comprising a gold bump over said horizontal outside, wherein said gold bump is connected to said first patterned metal layer.