High performance IC chip having discrete decoupling capacitors attached to its IC surface
View Patent ↗In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude μF, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components.
1. An integrated circuit device comprising:
a semiconductor substrate comprising a base surface and an active surface vertically spaced apart from and opposing said base surface, said active surface extending in a horizontal direction and having at least one active device therein;
multiple metal and dielectric layers over said semiconductor substrate;
a first contact pad over said active surface of said semiconductor substrate;
a second contact pad over said active surface of said semiconductor substrate;
a passivation layer over said multiple metal and dielectric layers, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact area of said first contact pad, and said first contact area is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact area of said second contact pad, and said second contact area is at a bottom of said second opening;
a power metal pad over said passivation layer and covered by a post-passivation layer comprising a polymer, said power metal pad having a first region and a second region, said second region being directly vertically over said first contact area, wherein said power metal pad is connected to said first contact area through said first opening, and said first region is not directly vertically over, and is horizontally offset from, said first opening and said first contact area such that said first region is directly attached to a wirebond through an opening in said post-passivation layer for connection made to a next level of packaging;
a ground metal pad over said passivation layer and covered by said post-passivation layer, said ground metal pad having a third region and a fourth region, said fourth region being directly vertically over said second contact area, wherein said ground metal pad is connected to said second contact area through said second opening, and the third region is not directly vertically over, and is horizontally offset from, said second opening and said second contact area such that said third region is directly attached to a wirebond through an opening in the post-passivation layer for connection made to said next level of packaging;
a capacitor over said post-passivation layer and said power and ground metal pads, said capacitor comprising a first terminal and a second terminal, said first terminal directly vertically over and connected through an opening in said post-passivation layer by a first solder joint to said second region, and said second terminal directly vertically over and connected through an opening in said post-passivation layer by a second solder joint to said fourth region.
2. The integrated circuit device according to claim 1 , wherein said ground metal pad further comprises a copper layer and a gold layer over said copper layer.
3. The integrated circuit device according to claim 1 , wherein said nitride comprises silicon nitride.
4. The integrated circuit device according to claim 1 , wherein said ground metal pad further comprises a copper layer and a nickel layer over said copper layer.
5. The integrated circuit device according to claim 1 , wherein said passivation layer further comprises an oxide.
6. The integrated circuit device according to claim 1 , wherein said passivation layer further comprises silicon oxide.
7. An integrated circuit device comprising:
a semiconductor substrate comprising a base surface and an active surface vertically spaced apart from and opposing said base surface, said active surface extending in a horizontal direction and having at least one active device therein;
multiple metal and dielectric layers over said semiconductor substrate;
a first contact pad over said active surface of said semiconductor substrate;
a passivation layer over said multiple metal and dielectric layers, wherein a first opening in said passivation layer is over a first contact area of said first contact pad, and said first contact area is at a bottom of said first opening, wherein said passivation layer comprises a nitride;
a second contact pad over said active surface of said semiconductor substrate, over said passivation layer and covered by a post-passivation layer comprising a polymer, said second contact pad having a first region and a second region, said second region being directly vertically over said first opening and said first contact area, said second contact pad being connected to said first contact area through said first opening, wherein said second contact pad comprises a first gold layer with a thickness greater than 1 micrometer, and wherein said first region is not directly vertically over, and is horizontally offset from, said first opening and said first contact area such that said first region is directly attached to a wirebond through an opening in said post-passivation layer;
a capacitor over said post-passivation layer and said second contact pad, said capacitor comprising a first terminal that is directly vertically over and connected through an opening in said post-passivation layer by a first solder joint to said second region of said second contact pad, thereby being electrically coupled to said first contact area.
8. The integrated circuit device according to claim 7 further comprising a third contact pad over said semiconductor substrate, wherein a second opening in said passivation layer is over a second contact area of said third contact pad, and said second contact area is at a bottom of said second opening, wherein said second contact area is configured to be wirebonded thereto for connection made to a next level of packaging.
9. The integrated circuit device according to claim 7 further comprising a third contact pad over said passivation layer, wherein said third contact pad is configured to be wirebonded thereto for connection made to a next level of packaging.
10. The integrated circuit device according to claim 9 , wherein said third contact pad comprises a second gold layer.
11. The integrated circuit device according to claim 7 further comprising a third contact pad over said semiconductor substrate, wherein a second opening in said passivation layer is over a second contact area of said third contact pad, and said second contact area is at a bottom of said second opening, and a fourth contact pad on said second contact area, wherein said fourth contact pad is configured to be wirebonded thereto for connection made to a next level of packaging.
12. The integrated circuit device according to claim 7 , wherein said capacitor comprises a decoupling capacitor.
13. The integrated circuit device according to claim 7 , wherein said nitride comprises silicon nitride.
14. The integrated circuit device according to claim 7 , wherein said passivation layer further comprises an oxide.
15. The integrated circuit device according to claim 7 , wherein said passivation layer further comprises silicon oxide.
16. An integrated circuit device comprising:
a semiconductor substrate comprising a base surface and an active surface vertically spaced apart from and opposing said base surface, said active surface extending in a horizontal direction and having at least one active device therein;
multiple metal and dielectric layers over said semiconductor substrate;
a first contact pad over said active surface of said semiconductor substrate;
a passivation layer over said multiple metal and dielectric layers, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact area of said first contact pad, and said first contact area is at a bottom of said first opening;
a second contact pad over said active surface of said semiconductor substrate, over said passivation layer and covered by a post-passivation layer comprising a polymer, said second contact pad having a first region and a second region, said second region being directly vertically over said first contact area, wherein said second contact pad is connected to said first contact area through said first opening, wherein a second opening in said post-passivation layer is over a second contact area of said second contact pad, and said second contact area is at a bottom of said second opening, and said first region is not directly vertically over, and is horizontally offset from, said first opening and said first contact area such that said first region is directly attached to a wirebond through an opening in said post-passivation layer for connection made to a next level of packaging;
a third contact pad over said active surface of said semiconductor substrate, over said passivation layer and covered by said post-passivation layer, said third contact pad having a third region and a fourth region, said fourth region being directly vertically over said second contact area, wherein said third contact pad is connected to said second contact area through said second opening, and said third region is not directly over, and is horizontally offset from, said second opening and said second contact area such that said third region is directly attached to a wirebond through an opening in said post-passivation layer for connection made to said next level of packaging;
a capacitor over said post-passivation layer, said capacitor having a terminal that is directly vertically over and connected through a second opening in said post-passivation layer to said second contact area; and
a solder joint between said second contact area and said terminal of said capacitor, wherein said solder joint connects said terminal to said second contact area.
17. The integrated circuit device according to claim 16 , wherein said second contact pad comprises a gold layer.
18. The integrated circuit device according to claim 16 , wherein said second contact pad comprises a copper layer.
19. The integrated circuit device according to claim 16 , wherein a ground voltage is applied to said first contact pad.
20. The integrated circuit device according to claim 16 , wherein a power supply voltage is applied to said first contact pad.
21. The integrated circuit device according to claim 16 , wherein said nitride comprises silicon nitride.
22. The integrated circuit device according to claim 16 , wherein said third contact pad comprises a gold layer.
23. The integrated circuit device according to claim 16 , wherein said capacitor comprises a decoupling capacitor.
24. The integrated circuit device according to claim 16 , wherein said post-passivation layer comprises polyimide.
25. The integrated circuit device according to claim 16 , wherein said post-passivation layer has a thickness between 2 and 150 micrometers.
26. The integrated circuit device according to claim 16 , wherein a ground voltage is applied to said first, second and third contact pads.
27. The integrated circuit device according to claim 16 , wherein a power supply voltage is applied to said first, second and third contact pads.
28. The integrated circuit device according to claim 16 , wherein said passivation layer further comprises an oxide.
29. The integrated circuit device according to claim 16 , wherein said passivation layer further comprises silicon oxide.
30. An integrated circuit device comprising:
a semiconductor substrate comprising a base surface and an active surface vertically spaced apart from and opposing said base surface, said active surface extending in a horizontal direction and having at least one active device therein;
multiple metal and dielectric layers over said semiconductor substrate;
a first contact pad over said active surface of said semiconductor substrate;
a passivation layer over said multiple metal and dielectric layers, wherein a first opening in said passivation layer is over a first contact area of said first contact pad, and said first contact area is at a bottom of said first opening, wherein said passivation layer comprises a nitride;
a second contact pad over said active surface of said semiconductor substrate, over said passivation layer and covered by a post-passivation layer comprising a polymer, said second contact pad having a first region and a second region, said second region being directly vertically over said first opening and said first contact area, said second contact pad being connected to said first contact area through said first opening, wherein said second contact pad comprises a first gold layer with a thickness greater than 1 micrometer, and wherein said first region is not directly vertically over, and is horizontally offset from, said first opening and said first contact area such that said first region is directly attached to a wirebond through an opening in said post-passivation layer for connection made to a next level of packaging;
a capacitor over said post-passivation layer and said second contact pad, said capacitor comprising a first terminal that is directly vertically over and connected through an opening in said post-passivation layer by a first solder joint to said second region of said second contact pad, thereby being electrically coupled to said first contact area; and
a third contact pad between said first solder joint and said second contact pad, wherein said third contact pad is finished with a solder wettable material comprising gold, wherein a contact area between said third contact pad and said second contact pad is not directly vertically over said first contact area.
31. The integrated circuit device according to claim 30 further comprising a fourth contact pad over said semiconductor substrate, wherein a second opening in said passivation layer is over a second contact area of said fourth contact pad, and said second contact area is at a bottom of said second opening, wherein said second contact area is configured to be wirebonded thereto for connection made to a next level of packaging.
32. The integrated circuit device according to claim 30 further comprising a fourth contact pad over said passivation layer, wherein said fourth contact pad is configured to be wirebonded thereto for connection made to a next level of packaging.
33. The integrated circuit device according to claim 30 further comprising a fourth contact pad over said semiconductor substrate, wherein a second opening in said passivation layer is over a second contact area of said fourth contact pad, and said second contact area is at a bottom of said second opening, and a fifth contact pad on said second contact area, wherein said fifth contact pad is configured to be wirebonded thereto for connection made to a next level of packaging.
34. The integrated circuit device according to claim 33 , wherein said fifth contact pad comprises a second gold layer.
35. The integrated circuit device according to claim 30 , wherein said capacitor comprises a decoupling capacitor.
36. The integrated circuit device according to claim 30 , wherein said nitride comprises silicon nitride.
37. The integrated circuit device according to claim 30 , wherein said passivation layer further comprises an oxide.
38. The integrated circuit device chip according to claim 30 , wherein said passivation layer further comprises silicon oxide.