Electronic device and chip package
View Patent ↗The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.
1. A chip package comprising:
a first chip;
a second chip;
a circuitry component;
a solder ball under a bottom surface of said circuitry component;
a solder bump under said first chip, wherein said solder bump connects said first chip and a top surface of said circuitry component; and
more than three gold bumps aligned in a line and connecting said first and second chips.
2. The chip package of claim 1 , wherein said solder bump has a height greater than that of said gold bumps.
3. A chip package comprising:
a circuitry component having top and bottom surfaces, wherein said top surface has a first region and a second region, said first region being substantially coplanar with said second region;
a first chip;
a second chip;
a first bump connecting said first chip and said second chip;
a second bump connecting said first chip and said second region, wherein said second chip is over said first region; and
a solder ball under said bottom surface.
4. The chip package of claim 3 , wherein said second bump has a height greater than that of said first bump plus said second chip.
5. The chip package of claim 3 , wherein said second chip is between said first chip and said first region.
6. The chip package of claim 3 , wherein said first bump has a principal material different from that of said second bump.
7. The chip package of claim 3 , wherein said first bump has a principal material comprising gold.
8. The chip package of claim 3 , wherein said first bump has a principal material comprising solder.
9. The chip package of claim 3 , wherein said second bump has a principal material comprising solder.
10. The chip package of claim 3 , wherein said first chip has a peripheral region and a center region, said peripheral region surrounding said center region, said first bump being under said center region, and said second bump being under said peripheral region.
11. The chip package of claim 3 , wherein said second region surrounds said first region.
12. The chip package of claim 3 , wherein said second bump is barrel-shaped.
13. The chip package of claim 3 , wherein said first bump is barrel-shaped.
14. The chip package of claim 3 , wherein said first bump comprises a post.
15. The chip package of claim 3 , wherein said circuitry component comprises a ball grid array substrate.
16. The chip package of claim 3 , wherein there is a space between said second chip and said first region.
17. A chip package comprising:
a circuitry component;
a first chip;
a second chip;
a first bump connecting said second chip and said first chip;
a second bump connecting said first chip and a top surface of said circuitry component,
wherein said second bump has a height greater than that of said first bump plus said second chip; and
a solder ball under a bottom surface of said circuitry component.
18. The chip package of claim 17 , wherein said second chip is between said first chip and said circuitry component.
19. The chip package of claim 17 , wherein said first bump has a principal material different from that of said second bump.
20. The chip package of claim 17 , wherein said first bump has a principal material comprising gold.
21. The chip package of claim 17 , wherein said first bump has a principal material comprising solder.
22. The chip package of claim 17 , wherein said second bump is barrel-shaped.
23. The chip package of claim 17 , wherein said first chip has a peripheral region and a center region, said peripheral region surrounding said center region, said first bump is under said center region, and said second bump is under said peripheral region.
24. The chip package of claim 17 , wherein there is a space between said second chip and said circuitry component.
25. The chip package of claim 17 , wherein said first bump is barrel-shaped.
26. The chip package of claim 17 , wherein said first bump comprises a post.
27. The chip package of claim 17 , wherein said circuitry component comprises a ball grid array substrate.
28. A chip package comprising:
a first chip;
a second chip;
a circuitry component;
a solder bump connecting said first chip and a top surface of said circuitry component;
a gold bump connecting said first and second chips; and
a solder ball under a bottom surface of said circuitry component.
29. The chip package of claim 17 , wherein said second bump has a principal material comprising solder.
30. The chip package of claim 28 , wherein said solder bump has a height greater than that of said gold bump plus said second chip.
31. The chip package of claim 29 , wherein said second chip is between said first chip and said circuitry component.
32. The chip package of claim 29 , wherein said first chip has a peripheral region and a center region, said peripheral region surrounding said center region, said gold bump being under said center region, and said solder bump being under said peripheral region.
33. The chip package of claim 29 , wherein said circuitry component comprises a ball grid array substrate.
34. The chip package of claim 29 , wherein there is a space between said second chip and said circuitry component.