Wirebond pad for semiconductor chip or wafer
View Patent ↗In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.
1. A semiconductor chip with a wirebonded wire, comprising:
a silicon substrate;
an active device in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
an interconnecting metallization structure over said first dielectric layer, wherein said interconnecting metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said interconnecting metallization structure comprises a copper pad having a top surface and a sidewall, wherein said top surface has a first region and a second region between said sidewall and said first region;
a second dielectric layer between said first and second metal layers;
a passivation layer over said interconnecting metallization structure, on said second region and over said first and second dielectric layers, wherein an opening in said passivation layer is over said first region;
an aluminum cap comprising a first portion directly over said first region and a second portion directly over said passivation layer, wherein said aluminum cap is connected to said copper pad through said opening in said passivation layer, and wherein said aluminum cap has a width greater than that of said opening in said passivation layer;
an adhesion/barrier layer on said aluminum cap; and
a gold layer on said adhesion/barrier layer and directly over said first and second portions of said aluminum cap, wherein said gold layer comprises a gold seed layer and an electroplated gold layer on said gold seed layer, wherein said electroplated gold layer has a thickness between 2 and 20 micrometers, and wherein said wirebonded wire is joined with said gold layer.
2. The semiconductor chip of claim 1 , wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip.
3. The semiconductor chip of claim 1 , wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip.
4. The semiconductor chip of claim 1 , wherein said adhesion/barrier layer comprises tantalum.
5. The semiconductor chip of claim 1 further comprising a polymer layer between said adhesion/barrier layer and said passivation layer, wherein said polymer layer has a thickness between 2 and 20 micrometers.
6. The semiconductor chip of claim 5 , wherein said polymer layer comprises polyimide.
7. The semiconductor chip of claim 1 further comprising a third dielectric layer on said gold layer, wherein an opening in said third dielectric layer is over said gold layer joined with said wirebonded wire.
8. The semiconductor chip of claim 1 , wherein said gold layer joined with said wirebonded wire is directly over said active device.
9. The semiconductor chip of claim 1 , wherein said adhesion/barrier layer comprises titanium.
10. The semiconductor chip of claim 1 , wherein said active device comprises a transistor.
11. A semiconductor chip with a wirebonded wire, comprising:
a silicon substrate;
an active device in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
an interconnecting metallization structure over said first dielectric layer, wherein said interconnecting metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said interconnecting metallization structure comprises a copper pad having a top surface and a sidewall, wherein said top surface has a first region and a second region between said sidewall and said first region;
a second dielectric layer between said first and second metal layers;
a passivation layer over said interconnecting metallization structure, on said second region and over said first and second dielectric layers, wherein an opening in said passivation layer is over said first region;
an adhesion/barrier layer over said first region and over said passivation layer; and
a gold layer on said adhesion/barrier layer, wherein said electroplated gold layer has a thickness between 2 and 20 micrometers wherein said gold layer comprises a gold seed layer and an electroplated gold layer on said gold seed layer, wherein said gold layer is connected to said copper pad through said opening in said passivation layer, wherein said gold layer comprises a first portion directly over said first region and a second portion directly over said passivation layer, and wherein said wirebonded wire is joined with said gold layer.
12. The semiconductor chip of claim 11 , wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip.
13. The semiconductor chip of claim 11 , wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip.
14. The semiconductor chip of claim 11 , wherein said adhesion/barrier layer comprises tantalum.
15. The semiconductor chip of claim 11 further comprising a polymer layer between said adhesion/barrier layer and said passivation layer, wherein said polymer layer has a thickness between 2 and 20 micrometers.
16. The semiconductor chip of claim 15 , wherein said polymer layer comprises polyimide.
17. The semiconductor chip of claim 11 further comprising a third dielectric layer on said gold layer, wherein an opening in said third dielectric layer is over said gold layer joined with said wirebonded wire.
18. The semiconductor chip of claim 11 , wherein said gold layer joined with said wirebonded wire is directly over said active device.
19. The semiconductor chip of claim 11 , wherein said adhesion/barrier layer comprises titanium.
20. The semiconductor chip of claim 11 , wherein said active device comprises a transistor.