Structure and manufacturing method of a chip scale package
A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.
1 . A chip package comprising:
a semiconductor device;
a substrate having a pad having an edge not covered by a mask; and
a bump between said semiconductor device and said substrate, wherein said bump is bonded to said pad.
2 . The chip package of claim 1 further comprising a post between said bump and said semiconductor device, wherein said post has a thickness of greater than 10 microns.
3 . The chip package of claim 2 , wherein said thickness is less than 100 microns.
4 . The chip package of claim 2 further comprising a barrier layer between said post and said semiconductor device.
5 . The chip package of claim 2 further comprising a metal layer between said post and said bump, wherein said metal layer has a surface on said post, said surface having a region not covered by said post.
6 . The chip package of claim 5 , wherein the distance between an edge of said metal layer and an edge of said post is greater than 0.2 microns.
7 . The chip package of claim 1 , wherein said bump comprises solder.
8 . The chip package of claim 1 , wherein said semiconductor device comprises a pad and a passivation layer, said post over said pad being exposed by an opening in said passivation layer, and wherein said bump is over said pad.
9 . The chip package of claim 1 further comprising a barrier between said bump and said pad.
10 . The chip package of claim 1 , wherein said mask comprises a solder mask.