Graphic memory management with invisible hardware-managed page faulting
View Patent ↗A computer system in which a graphics accelerator unit manages page faulting of texture data invisibly to the host processor.
1. A computer system, comprising:
a graphics accelerator unit which manages page faulting of texture data invisibly to the host processor.
2. A computer system, comprising:
a graphics accelerator unit which manages page faulting of texture data, from main memory used by at least one host processor into a dedicated graphics memory, invisibly to the host processor, except when said graphics accelerator unit calls for data which has not recently been present in said main memory.
3. The system of claim 2 , wherein said graphics accelerator unit also includes a PCI/AGP interface, DMA controllers, SGRAM/SDRAM, a RAMDAC, and a video stream interface.
4. The system of claim 2 , wherein said dedicated graphics memory is SGRAM/SDRAM to which the unit has read-write access through its frame buffer and local buffer ports.
5. The system of claim 2 , wherein said host processor is operatively connected to receive inputs from input devices through an interface manager chip which provides an interface to various ports and registers.
6. A computer system, comprising:
at least one CPU, operatively connected to have read/write access to a main memory;
first memory management logic, which virtualizes said main memory with reference to at least one bulk storage unit; and
a graphics accelerator unit, comprising rendering accelerator logic, dedicated graphics memory, and a second memory management unit which manages texture data for said accelerator logic and performs page faulting of said texture data, invisibly to said CPU.
7. The system of claim 6 , wherein said first memory management logic is a bridge controller.
8. The system of claim 6 , wherein said bulk storage unit is a mass storage disk drive.
9. The system of claim 6 , wherein said accelerator unit determines where the page is located in host physical memory to be manipulated is located; and wherein said accelerator unit determines which page out of the working set to use, marks this page the most recently used page, and updates the page tables for the new page and remove any reference to the page just bumped out of memory.
10. A computer system, comprising:
at least one CPU, operatively connected to have read/write access to a main memory; first memory management logic, which virtualizes said main memory with reference to at least one bulk storage unit; and a graphics accelerator unit, comprising rendering accelerator logic, dedicated graphics memory, and a second memory management unit which manages texture data for said accelerator logic and performs page faulting of said texture data, invisibly to said CPU;
wherein said graphics accelerator unit also includes a PCI/AGP interface, DMA controllers, SGRAM/SDRAM, a RAMDAC, and a video stream interface.
11. A computer system, comprising:
at least one CPU, operatively connected to have read/write access to a main memory; first memory management logic, which virtualizes said main memory with reference to at least one bulk storage unit; and a graphics accelerator unit, comprising rendering accelerator logic, dedicated graphics memory, and a second memory management unit which manages texture data for said accelerator logic and performs page faulting of said texture data, invisibly to said CPU; wherein said second memory management unit also manages texture storage in the main memory in addition to managing texturecstorage in normal texture memory.