IP Library › Assignment 048947/0592
Patent Assignment
Reel/Frame 048947/0592

Assignment of Assignor's Interest

Recorded: 2019-04-19 Pages: 12
Assignor
ZIILABS INC., LTD
Executed: 2019-04-18
Assignee
RPX CORPORATION
ONE MARKET PLAZA, STEUART TOWER, SUITE 1100, SAN FRANCISCO, CALIFORNIA, 94105
Covered Properties (65)
Rendering System with Mini-Patch Retrieval from Local Texture Storage
Patent: 6,111,584 →
Application: 08/657,945 →
Triangle Clipping for 3D Graphics
Patent: 7,215,344 →
Application: 09/133,741 →
Publication: US 2002/0030693
Dma System for Contiuing Transferring Additional Data When Requested to Avoid an Additional Set Up Time
Patent: 6,253,261 →
Application: 09/176,594 →
3D Graphics Rendering with Selective Read Suspend
Patent: 6,977,649 →
Application: 09/280,250 →
Method and Apparatus for Transporting Information to a Graphic Accelerator Card
Patent: 6,313,845 →
Application: 09/345,678 →
Graphics Processor with Texture Memory Allocation System
Patent: 7,518,616 →
Application: 09/353,887 →
Graphics Processing with Transcendental Function Generator
Patent: 6,181,355 →
Application: 09/354,083 →
Graphic Memory Management with Invisible Hardware-Managed Page Faulting
Patent: 7,710,425 →
Application: 09/591,225 →
Autonomous Address Translation in Graphic Subsystem
Patent: 7,050,061 →
Application: 09/591,226 →
Texture Caching with Change of Update Rules at Line End
Patent: 6,587,113 →
Application: 09/591,228 →
Multi-Pool Texture Memory Management
Patent: 6,650,333 →
Application: 09/591,229 →
Texture Download Dma Controller Synching Multiple Independently-Running Rasterizers
Patent: 6,677,952 →
Application: 09/591,230 →
Doubly-Virtualized Texture Memory
Patent: 6,683,615 →
Application: 09/591,231 →
Direct-Mapped Texture Caching with Concise Tags
Patent: 7,061,500 →
Application: 09/591,532 →
Texture Caching with Background Preloading
Patent: 6,744,438 →
Application: 09/591,533 →
Graphics Request Buffer Caching Method
Patent: 6,677,954 →
Application: 10/010,469 →
Rasterizer Edge Function Optimizations
Patent: 7,106,323 →
Application: 10/071,895 →
Publication: US 2003/0128204
Vector Instruction Set
Patent: 6,788,303 →
Application: 10/085,466 →
Publication: US 2002/0130874
Antialias Mask Generation
Patent: 6,819,332 →
Application: 10/085,467 →
Publication: US 2002/0130886
Tile Relative Origin for Plane Equations
Patent: 6,900,800 →
Application: 10/085,487 →
Publication: US 2002/0130863
Parameter Circular Buffers
Patent: 6,791,559 →
Application: 10/085,976 →
Publication: US 2002/0126126
Yield Enhancement of Complex Chips
Patent: 7,187,383 →
Application: 10/086,980 →
Publication: US 2003/0164830
Configurable Pipe Delay with Window Overlap for Ddr Receive Data
Patent: 6,950,350 →
Application: 10/117,663 →
Multiple simultaneous bin sizes
Patent: 9,098,943 →
Application: 10/903,671 →
Sequencer with Async Simd Array
Patent: 8,144,156 →
Application: 10/952,225 →
Multi-Sample Antialiasing Optimization via Edge Tracking
Patent: 9,218,689 →
Application: 10/952,358 →
Shader with Global and Instruction Caches
Patent: 8,643,659 →
Application: 10/958,758 →
Stochastic Super Sampling or Automatic Accumulation Buffering
Patent: 8,223,157 →
Application: 11/005,522 →
Systems and Methods for Reducing Noise in Video Streams
Patent: 9,041,834 →
Application: 13/622,977 →
Publication: US 2014/0078347
Shader with Global and Instruction Caches
Application: 14/172,839 →
Publication: US 2014/0354646
Systems and Methods for Reducing Noise in Video Streams
Patent: 9,615,039 →
Application: 14/716,336 →
Publication: US 2015/0256772
Multiple Simultaneous Bin Sizes
Patent: 9,349,215 →
Application: 14/815,860 →
Multi-Sample Antialiasing Optimization via Edge Tracking
Patent: 9,406,168 →
Application: 14/976,918 →
Multiple Simultaneous Bin Sizes
Patent: 9,990,768 →
Application: 15/162,526 →
Multi-Sample Antialiasing Optimization via Edge Tracking
Patent: 9,679,364 →
Application: 15/225,776 →
Systems and Methods for Reducing Noise in Video Streams
Application: 15/476,764 →
Publication: US 2017/0280073
Multi-Sample Antialiasing Optimization via Edge Tracking
Patent: 9,916,643 →
Application: 15/620,708 →
Multiple Simultaneous Bin Sizes
Application: 15/996,463 →
Gigi Graphics Processor 1
Application: 60/008,816 →
Gamma Clipping for 3D Graphics
Application: 60/071,590 →
Method and System for Transporting Information to a Graphic Accelerator Card
Application: 60/091,401 →
Graphics Processor with Texture Memory Allocation System
Application: 60/093,159 →
Graphics Processing with Transcendental Function Generator
Application: 60/093,185 →
Read Monitor Unit
Application: 60/109,733 →
Graphics Accelerator with Various Independent Improvements in Texture Caching and in Texture Virtualization
Application: 60/138,248 →
Graphics Accelerator with Various Independent Improvements in Texture Caching and in Texture Virtualization
Application: 60/138,350 →
Multi-Pool Texture Memory Management
Application: 60/143,654 →
Doubly-Virtualized Texture Memory
Application: 60/143,655 →
Texture Download Dma Controller Synching Multiple Independently-Mming Rasterizer
Application: 60/143,660 →
Texture Caching with Change of Update Rules at Line End
Application: 60/143,661 →
Direct-Mapped Texture Caching with Concise Tags
Application: 60/143,712 →
Autonomous Address Translation in Graphics Subsystem
Application: 60/143,825 →
Texture Caching with Background Preloading
Application: 60/143,826 →
Graphics request buffer caching methodology
Application: 60/255,673 →
Rasteriser edge function optimisations
Application: 60/267,265 →
Vector instruction set
Application: 60/271,795 →
Antialias mask generation
Application: 60/271,796 →
Tile relative origin for plane equations
Application: 60/271,851 →
Parameter circular buffers
Application: 60/272,516 →
Configurable pipe delay with window overlap for DDR SDRAM receive data
Application: 60/346,518 →
Multi sample antialiasing optimization via edge tracking
Application: 60/533,491 →
Shader with global and instruction cache
Application: 60/533,532 →
Sequencer with async SIMD array
Application: 60/533,736 →
Stochastic super sampling or automatic accumulation buffering
Application: 60/533,789 →
Multiple simultaneous bin sizes
Application: 60/533,813 →
Related Assignments (11)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Mar 10, 2014
From: 3DLABS INC., LTD.
To: ZIILABS INC., LTD.
Reel/Frame 032423/0468 →
Change of Name Mar 10, 2014
From: 3DLABS INC., LTD.
To: ZIILABS INC., LTD.
Reel/Frame 032423/0466 →
Change of Name Mar 10, 2014
From: 3DLABS INC., LTD.
To: ZIILABS INC., LTD.
Reel/Frame 032423/0457 →
Change of Name Apr 1, 2014
From: 3DLABS INC., LTD.
To: ZIILABS INC., LTD.
Reel/Frame 032588/0125 →
Assignment of Assignor's Interest Aug 5, 2020
From: RPX CORPORATION
To: MEDIATEK INC.
Reel/Frame 054107/0830 →
Release of Lien on Patents Aug 14, 2020
From: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
To: RPX CORPORATION
Reel/Frame 053498/0067 →
Assignment of Assignor's Interest Aug 21, 2020
From: RPX CORPORATION
To: MEDIATEK INC.
Reel/Frame 054152/0888 →
Patent Security Agreement Oct 23, 2020
From: RPX CLEARINGHOUSE LLC; RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 054198/0029 →
Patent Security Agreement Oct 23, 2020
From: RPX CLEARINGHOUSE LLC; RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 054244/0566 →
Assignment of Assignor's Interest Mar 18, 2021
From: MEDIATEK INC.
To: XUESHAN TECHNOLOGIES INC.
Reel/Frame 056593/0167 →
Release of Security Interest in Specified Patents May 10, 2022
From: BARINGS FINANCE LLC
To: RPX CLEARINGHOUSE LLC
Reel/Frame 059925/0652 →