Direct-mapped texture caching with concise tags
View Patent ↗A graphics system architecture, in which condensed cache tags for texture are achieved by a remapping operation which exploits the relation between the level-of-detail parameter of mip mapping and the maximum resolution.
1. A graphics processing method, comprising the steps of:
(a.) caching texture memory fetches, using a cache tag assignment which is unique mapped, the cache tag assignment having a tag length and mip mapping addresses, while
(b.) generating condensed cache tags, by removing two bits from the tag length by means of a remapping which exploits different address resolutions implied by level of detail settings in different mip mapping processes to re-encode the mip mapping addresses
(c.) and using the condensed tags for caching step (a.),
(d.) coding a map level identifier so that
a largest map level uses 1 bit to designate a map level and ((m−i)+(n−j)) bits to specify said addresses on said x- and y-axis,
a second largest map level uses 3 bits to designate a map level and ((m−i)+(n−j)+2) bits to specify the addresses on the x-axis and y-axis, and
successively smaller map levels use greater than 3 bits to designate a map level and less than ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis.
2. A graphics processing method, comprising caching texture memory fetches using a cache tag assignment in which a unique relation between a mip-mapping-level-of-detail parameter and coordinate bits defines a smaller tag address for any given memory address;
wherein a map level identifier is coded so that
a largest map level uses 1 bit to designate a map level and ((m−i)+(n−j)) bits to specify said addresses on said x- and y-axis,
a second largest map level uses 3 bits to designate a map level and ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis, and
successively smaller map levels use greater than 3 bits to designate a map level and less than ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis.
3. The graphics processing method of claim 2 , wherein the cache tag assignment is generated by combining a mip-map-level-of-detail parameter which can have at least 2 J−1 +1 different values together with coordinate bits which can have as many as 2 K different values into fewer than J+2K bits without loss of information; wherein J represents the number of bits for a level of detail and K represents the number of bits for arbitrary coordinate values.
4. The graphics processing method of claim 2 , wherein the cache tag assignment is generated by combining a first parameter which can have at least 2 J−1 +1 different values together with coordinate bits which can have as many as 2 K different values into fewer than J+2K bits without loss of information;
wherein the first parameter and the coordinate bits are three-dimensional coordinates; and
wherein J represents the number of bits for a level of detail and K represents the number of bits for arbitrary coordinate values.
5. A method of generating condensed cache tags, comprising the steps of:
(a.) concatenating a texel address on an x- and y-axis with a map level identifier, where addresses on the x-axis can require m bits, addresses on the y-axis can require n bits, and the map-level identifier can require p bits;
(b.) if two caches are being used for odd/even maps, deleting a least significant bit of the map level identifier;
(c.) if texels are being stored in the cache in 2 i ×2 j patches, such that i and j represent a texel's address on the x- and y-axis respectively and said address having i and j least significant bits, deleting the i least significant bits of the address on the x-axis and the j least significant bits of the address on the y-axis; and
(d.) coding said map level identifier so that
a largest map level uses 1 bit to designate a map level and ((m−i)+(n−j)) bits to specify said addresses on said x- and y-axis,
a second largest map level uses 3 bits to designate a map level and ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis, and
successively smaller map levels use greater than 3 bits to designate a map level and less than ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis.
6. A graphics processing method, comprising the steps of:
(a.) caching texture memory fetches, using a cache tag assignment which is unique mapped, while
(b.) generating condensed cache tags, by means of a remapping which exploits different address resolutions implied by level of detail settings in different mip mapping processes to re-encode mip mapping addresses into a length which is only one bit longer than a maximum condensed length of a spatial address
(c.) and using the condensed tags for caching step (a.)
(d.) coding a map level identifier so that
a largest map level uses 1 bit to designate a map level and ((m−i)+(n−j)) bits to specify said addresses on said x- and y-axis,
a second largest map level uses 3 bits to designate a map level and ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis, and
successively smaller map levels use greater than 3 bits to designate a map level and less than ((m−i)+(n−j)−2) bits to specify the addresses on the x-axis and y-axis.