Shader with global and instruction caches
View Patent ↗An instruction cache and data cache used to virtualize the storage of global data and instructions used by graphics shaders. Present day hardware design stores the global data and instructions used by the shaders in a fixed amount of registers or writable control store (WCS). However, this traditional approach limits the size and the complexity of the shaders that can be supported. By virtualizing the storage of the global data and instructions, the amount of global or state memory available to the shader and the length of the shading programs are no longer constrained by the physical on-chip memory.
1. A 3D graphics accelerator comprising:
a fragment shading unit running multiple threads;
a first on-chip cache, internal to said fragment shading unit, which stores cached instructions to be executed by said fragment shading unit;
wherein the fragment shading unit first checks for data in said first cache, and if a miss occurs, then said fragment shading unit reads data from an external memory; and
a second on-chip cache, internal to said fragment shading unit, which stores global data which can affect multiple fragments being shaded by said fragment shading unit;
wherein neither fragment data nor texture data is routed through said first cache nor through said second cache;
whereby said fragment shading unit can switch operations between threads in a lightweight manner.
2. The accelerator of claim 1 , further comprising a memory arbiter that manages virtual memory and performs data swapping if a miss occurs.
3. The accelerator of claim 1 further comprising a third cache being configured to handle data other than the instructions and the global data.
4. A 3D graphics accelerator comprising:
a fragment shading unit running multiple threads;
a first on-chip cache, internal to said fragment shading unit, which stores data used by said fragment shading unit;
wherein the fragment shading unit first checks for data in said first cache, and if a miss occurs, then said fragment shading unit reads data from an external memory;
wherein said fragment shading unit also includes a second on-chip cache internal to said fragment shading unit; and
wherein data used by said fragment shading unit include instructions and global data; and wherein said instructions are stored in said first cache and said global data is stored in said second cache.
5. The accelerator of claim 4 , wherein said first and second caches are accessible in parallel.
6. A computer system for 3D graphics processing comprising:
a host processor; and
a 3D graphics accelerator comprising:
a fragment shading unit running multiple threads and including a first on-chip cache that stores cached instructions to be executed by said fragment shading unit;
wherein the first cache is included within said fragment shading unit, and wherein an external virtual memory stores a portion of the data used by said fragment shading unit;
wherein a second on-chip cache is included within said fragment shading unit, the second cache storing global data which can affect multiple fragments being shaded by said fragment shading unit;
whereby said fragment shading unit can switch operations between threads in a lightweight manner.
7. The system of claim 6 , wherein said graphics accelerator further comprises a memory arbiter that manages said virtual memory and performs data swapping if a miss occurs.
8. The system of claim 6 further comprising a third cache which is configured to handle data other than the instructions and the global data.
9. A computer system for 3D graphics processing, comprising:
a host processor; and
a 3D graphics accelerator comprising:
a fragment shading unit which runs multiple threads, and which includes a first on-chip cache that stores data used by said fragment shading unit;
wherein the first cache is included within said fragment shading unit, and wherein an external virtual memory stores a portion of the data used by said fragment shading unit;
whereby said fragment shading unit can switch operations between threads in a lightweight manner;
wherein said fragment shading unit also includes a second on-chip cache within the fragment shading unit; and
wherein data used by said fragment shading unit includes instructions and global data; and wherein said instructions are stored in said first cache and said global data is stored in said second cache.
10. The system of claim 9 , wherein said first and second caches are accessible in parallel.
11. A method for 3D graphics processing, comprising the steps of: in a fragment shading unit of a graphics accelerator,
performing shading operations using instructions, fragment data, texture data, and global data;
caching said instructions in a first on-chip cache, the first cache being included internal to the fragment shading unit;
caching said global data in a second on-chip cache, the second cache too being included internal to the fragment shading unit;
suspending the current thread if the required data is unavailable from the on-chip cache in time; and
accessing the data from a virtual memory when the required data is unavailable from the on-chip cache;
wherein neither said fragment data nor said texture data is normally cached in said first cache or said second cache.
12. The method of claim 11 , wherein said graphics accelerator further comprises a memory arbiter that manages the virtual memory and performs data swapping from the virtual memory if a miss occurs.
13. The method of claim 11 , wherein the size and complexity of said fragment shading unit are not constrained by physical on-chip storage.
14. The method of claim 11 , wherein said graphics accelerator also comprises a third cache being configured to handle fragment data.
15. A method for 3D graphics processing, comprising the steps of: in a fragment shading unit of a graphics accelerator,
storing data in a first on-chip cache, the first cache being included internal to the fragment shading unit;
suspending the current thread if the required data is unavailable from the on-chip cache in time; and
accessing the data from a virtual memory when the required data is unavailable from the on-chip cache;
wherein said fragment shading unit also comprises a second on-chip cache; and
wherein data used by said fragment shading unit include instructions and global data; and wherein said instructions are stored in said first cache and said global data is stored in said second cache.
16. The method of claim 15 , wherein said first and second caches are accessible in parallel.
17. A fragment shading unit comprising:
a fragment processor;
a sequencer;
an internal first on-chip cache;
an internal second on-chip cache;
wherein the sequencer and the fragment processor check for data in the first cache and second cache;
wherein said data comprises instructions in the first cache and global data used by the instructions in the second cache, the first and second caches normally not comprising fragment or texture data; and
wherein if a cache miss occurs for a thread, the thread is suspended and said data is accessed in a memory external to the fragment shading unit.
18. The fragment shading unit of claim 17 , wherein the memory external to the fragment shading unit comprises virtual memory.
19. A fragment shading unit, comprising:
a fragment processor;
a sequencer;
an internal first on-chip cache;
an internal second on-chip cache;
wherein the sequencer and the fragment processor check for data in the first cache and second cache;
wherein if a cache miss occurs for a thread, the thread is suspended and said data is accessed in a memory external to the fragment shading unit; and
wherein said data comprises instructions in the first cache and global data used by the instructions in the second cache.
20. The fragment shading unit of claim 19 , wherein the first cache is an instruction cache.