Patent Assignment
Reel/Frame 032588/0125
Change of Name
Recorded: 2014-04-01
Pages: 4
Assignor
3DLABS INC., LTD.
Executed: 2011-01-06
Assignee
ZIILABS INC., LTD.
CLARENDON HOUSE; 2 CHURCH STREET, HAMILTON, HM 11, BERMUDA
Covered Properties
(76)
Graphics Subsystem with Smart Direct-Memory-Access Operation
Patent:
5,777,629 →
Application:
08/409,716 →
Graphics System with Color Space Double Buffering
Patent:
5,742,796 →
Application:
08/409,748 →
Graphics Subsystem with Fast Clear Capability
Patent:
5,805,868 →
Application:
08/410,100 →
Graphics Subsystem with Coarse Subpixel Correction
Patent:
5,594,854 →
Application:
08/410,220 →
Three-Dimensional Graphics Subsystem with Enhanced Support for Graphical User Interface
Patent:
5,701,444 →
Application:
08/410,303 →
Integrated Graphics Subsystem with Message-Passing Architecture
Patent:
6,025,853 →
Application:
08/410,345 →
Graphics Subsystem with Slaveable Rasterizer
Patent:
5,815,166 →
Application:
08/410,354 →
Self-Clocking Pipeline Register
Patent:
5,534,796 →
Application:
08/427,076 →
System Usilizing Bios-Compatible High Performance Video Controller Being Default Controller at Boot-Up and Capable of Switching to Another Graphics Controller After Boot-Up
Patent:
5,799,204 →
Application:
08/432,106 →
System and Method for Controlling a Slave Processor
Patent:
5,878,216 →
Application:
08/432,272 →
Fifo Logical Addresses for Control and Error Recovery
Patent:
5,760,792 →
Application:
08/432,313 →
Vertex List Management System
Patent:
5,801,714 →
Application:
08/432,314 →
Parallel-Processor Graphics Architecture
Patent:
5,794,016 →
Application:
08/570,088 →
Graphics Pre-Processing and Rendering System
Patent:
5,764,228 →
Application:
08/640,514 →
Graphics Rendering System with Reconfigurable Pipeline Sequence
Patent:
5,798,770 →
Application:
08/640,620 →
Rendering Architecture with Selectable Processing of Multi-Pixel Spans
Patent:
5,764,243 →
Application:
08/640,662 →
Serial Rendering System with Auto-Synchronization on Frame Blanking
Patent:
5,727,192 →
Application:
08/641,472 →
Graphics System with Optimized Use of Unified Local and Frame Buffers
Patent:
6,348,919 →
Application:
08/659,132 →
Peer-To-Peer Parallel Processing Graphics Accelerator
Patent:
5,917,502 →
Application:
08/761,104 →
Dynamically Reconfigurable Multi-Function Pci Adapter Device
Patent:
5,960,213 →
Application:
08/763,855 →
Apparatus and Method for Signal Handling on Gtl-Type Buses
Patent:
5,852,372 →
Application:
08/803,157 →
Method and Apparatus for Texture Transmission and Storage
Patent:
6,285,373 →
Application:
08/823,753 →
Graphics Processing with Efficient Vector Drawing Efficient Stroking of Vectors with Arbitrary Endpoints
Patent:
6,529,196 →
Application:
08/825,259 →
High-Speed Video Frame Buffer Using Single Port Memory Chips
Patent:
5,864,512 →
Application:
08/832,708 →
Removable Circuit Board with Ducted Cooling
Patent:
5,822,188 →
Application:
08/835,694 →
Hardware-Accelerated Photoreal Rendering
Patent:
6,690,369 →
Application:
08/904,715 →
Direct Access to Slave Processing by Unprotected Application Using Context Saving and Restoration
Patent:
5,794,037 →
Application:
08/922,419 →
Graphics Processing with Efficient Clipping
Patent:
5,986,669 →
Application:
08/926,120 →
Multiple Display Synchronization Apparatus and Method
Patent:
6,046,709 →
Application:
09/007,615 →
Scalable Graphics Processor Architecture
Patent:
6,088,043 →
Application:
09/070,162 →
High Speed Video Frame Buffer
Patent:
6,278,645 →
Application:
09/129,293 →
Optimization of a Graphics Processor System When Rendering Images
Patent:
6,243,107 →
Application:
09/131,562 →
Triangle Clipping for 3D Graphics
Bit Blt with Multiple Graphics Processors
Patent:
6,377,266 →
Application:
09/133,744 →
Dma System for Contiuing Transferring Additional Data When Requested to Avoid an Additional Set Up Time
Patent:
6,253,261 →
Application:
09/176,594 →
Integrated Graphics Subsystem with Message-Passing Architecture
Patent:
6,154,223 →
Application:
09/207,800 →
Peer-To-Peer Parallel Processing Graphics Accelerator
Patent:
6,046,752 →
Application:
09/246,399 →
Buck Converter with Parallel Switches
Patent:
6,184,666 →
Application:
09/259,202 →
Dynamic Write-Order Organizer
Patent:
6,433,787 →
Application:
09/266,052 →
System for Reducing Aliasing on a Display Device
Patent:
7,616,200 →
Application:
09/329,557 →
Method and Apparatus for Transporting Information to a Graphic Accelerator Card
Patent:
6,313,845 →
Application:
09/345,678 →
System for Displaying a Television Signal on a Computer Monitor
Patent:
6,459,453 →
Application:
09/353,419 →
Wide Instruction Word Graphics Processor
System for Processing Vertices from a Graphics Request Stream
Patent:
6,188,410 →
Application:
09/353,432 →
Multi-Processor Graphics Accelerator
Patent:
6,476,816 →
Application:
09/353,495 →
Graphics Processor with Texture Memory Allocation System
Patent:
7,518,616 →
Application:
09/353,887 →
Data Sequencer with Mux Select Input for Converting Input Data Stream and to Specific Output Data Stream Using Two Exclusive-or Logic Gates and Counter
Patent:
6,480,913 →
Application:
09/353,894 →
Graphics Processing System with Multiple Strip Breakers
Patent:
6,518,971 →
Application:
09/353,912 →
Graphics Processing with Transcendental Function Generator
Patent:
6,181,355 →
Application:
09/354,083 →
Apparatus and Method of Directing Graphical Data to a Display Device
Patent:
6,157,393 →
Application:
09/354,462 →
Graphics Processor for Stereoscopically Displaying a Graphical Image
Patent:
6,674,440 →
Application:
09/533,158 →
Variable Stride Circle Rendering Apparatus and Method
Patent:
6,700,576 →
Application:
09/535,358 →
Graphics Request Buffer Caching Method
Patent:
6,677,954 →
Application:
10/010,469 →
Rasterizer Edge Function Optimizations
Planar Byte Memory Organization with Linear Access
Vector Instruction Set
Antialias Mask Generation
Tile Relative Origin for Plane Equations
Parameter Circular Buffers
Graphics Engine with Isochronous Context Switching
High Quality Antialiased Lines with Dual Sampling Pattern
Same Tile Method
In-Circuit Test Using Scan Chains
Auto-Disable Receive Control for Ddr Receive Strobes
Configurable Pipe Delay with Window Overlap for Ddr Receive Data
Patent:
6,950,350 →
Application:
10/117,663 →
System and Method for Fast Gradient Pixel Clears in Graphics Rendering
Patent:
7,466,319 →
Application:
10/163,793 →
Parallel Phased Switch Control
Patent:
6,597,157 →
Application:
10/164,172 →
System and Method for Reordering Fragment Data Based Upon Rasterization Direction
Patent:
6,766,410 →
Application:
10/166,155 →
System and Method for Optimizing Performance in a Four-Bank Sdram
Patent:
6,667,930 →
Application:
10/172,461 →
Multisample Dithering with Shuffle Tables
System and Method for Rasterization Through Approximation
Patent:
7,301,540 →
Application:
10/634,379 →
Power Converter Feedback Circuit
Patent:
7,368,831 →
Application:
10/657,053 →
Multisample Dithering with Shuffle Tables
Order-Independent 3D Graphics Binning Architecture
Patent:
7,505,036 →
Application:
10/903,193 →
State Tracking Methodology
Patent:
7,385,608 →
Application:
10/917,427 →
Stochastic Super Sampling or Automatic Accumulation Buffering
Patent:
8,223,157 →
Application:
11/005,522 →
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.