IP Library › Granted Patent US 7,050,061
Granted Patent B1
US 7,050,061 · App. 09/591,226 · Granted May 23, 2006

Autonomous address translation in graphic subsystem

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Quick Facts
Patent No.
US 7,050,061
App. No.
09/591,226
Granted
May 23, 2006
Kind
B1
Abstract

A texture caching controller, located on the graphics card, handles address logical-to-physical translation for texture addresses which are not downloaded to level-1 memory due to low use or dynamically changing values. This offloads texture memory management duties from the host.

Claims (4)

1. A graphics processing chip, comprising:

a graphics accelerator comprising rendering acceleration logic; and

a texture memory management function, integrated on said chip, which manages both texture storage in host memory and also texture storage in normal texture memory.

2. The chip of claim 1 , wherein said texture memory management function is able to read noncontiguous textures directly from said main memory.

Assignments (4)
PATENT SECURITY AGREEMENT Recorded Oct 23, 2020
From: RPX CLEARINGHOUSE LLC; RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 054198/0029 →
PATENT SECURITY AGREEMENT Recorded Oct 23, 2020
From: RPX CLEARINGHOUSE LLC; RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 054244/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2019
From: ZIILABS INC., LTD
To: RPX CORPORATION
Reel/Frame 048947/0592 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2012
From: 3DLABS LTD., A CORPORATION ORGANIZED UNDER THE LAWS OF GREAT BRITAIN
To: ZIILABS INC. LTD., A CORPORATION ORGANIZED UNDER THE LAWS OF BERMUDA
Reel/Frame 029299/0659 →