IP Library Granted Patent US 6,970,469
Granted Patent B1
US 6,970,469 · App. 09/601,695 · Granted Nov 29, 2005

Scheduling means for data switching apparatus

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Quick Facts
Patent No.
US 6,970,469
App. No.
09/601,695
Granted
Nov 29, 2005
Kind
B1
Abstract

A scheduling means for data switching apparatus includes a plurality of input ports and a plurality of output ports, the scheduling means capable of processing a plurality of interconnection requests, each requesting interconnection between a sub-set of the input ports and a sub-set of respective the output ports, and each request having a respective priority level which is one of a predetermined number of priority levels. The scheduling means includes determination means for determining a first set of requests selected from the plurality of requests, according to the respective priority levels; a first pipeline stage for receiving only the first set of requests am satisfying at least one of the first set of requests; a priority mixer for determining a further set of requests independently of the priority levels, the further set including requests of the first set which were not satisfied and requests included in the plurality of requests which were not part of the first set and which are of any of the priority levels, and an additional pipeline stage for identifying requests in the further set which can be satisfied, and for satisfying the identified requests.

Claims (12)

1. Scheduling means for data switching apparatus having a plurality of input ports and a plurality of output ports, the scheduling means capable of processing a plurality of interconnection requests, each request requesting interconnection between a subset of said input ports and a subset of respective said output ports, and each request having a respective priority level (Pi) which is one of a predetermined number of priority levels; the scheduling means comprising:

determination means for determining a first set of said requests selected from the plurality of requests, according to said respective priority levels; and

a first pipeline stage for receiving only said first set of requests and satisfying at least one of the first set of requests;

a priority mixer for determining a further set of said requests independently of said priority levels, the further set including requests of said first set which were not satisfied and requests included in said plurality of requests which were not part of said first set and which are of any of said priority levels; and

an additional pipeline stage for identifying requests in said further set which can be satisfied, and for satisfying the identified requests.

2. Scheduling means according to claim 1 wherein said determination means at any time determines said first set of requests as having the same priority level and wherein said priority level is a selected priority level.

3. Scheduling means according to claim 2 wherein the determination means varies the selected priority level with time, and wherein the proportion of time for which the selected priority level takes each of said predetermined number of priority levels is a respective predetermined proportion of time.

4. Scheduling means according to claim 1 further comprising at least one further pipeline stage receiving the requests not satisfied by the additional pipeline stage, a first of the at least one further pipeline stage receiving the requests not satisfied by the additional pipeline stage, and each of the other at least one further pipeline stages receiving the requests not satisfied by a preceding further pipeline stage.

5. Scheduling means according to claim 4 further comprising priority mixer provided before any of said further pipeline stages.

6. Scheduling means according to claim 1 which employs a data array (CV 1 , CV 0 ) defining connections, each of said pipeline stages satisfying said requests by modifying said data array.

7. Scheduling means according to claim 6 wherein upon receiving instructions specifying predetermined connections between at least two of the ports, said data array (CV 1 , CV 0 ) is modified to include said predetermined connections.

8. Scheduling means according to claim 1 , further comprising means which, upon receiving instructions to inhibit connections to or from any of the input or output ports, modifies the inputs to the first pipeline stage and priority mixer to prevent connections to or from said inhibited ports.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
RELEASE OF SECURITY INTEREST Recorded May 18, 2012
From: KREOS CAPITAL III (LUXEMBOURG) S.A.R.L
To: MICRON TECHNOLOGY, INC
Reel/Frame 028233/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2012
From: VIRTENSYS LIMITED
To: MICRON TECHNOLOGY, INC
Reel/Frame 028037/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2011
From: XYRATEX TECHNOLOGY LIMITED
To: VIRTENSYS LIMITED
Reel/Frame 027268/0610 →