Method for modulating a basic clock signal for digital circuits and clock modulator for implementing the method

1. A method for modulating a basic clock signal for digital circuits, in which distances between adjacent switching edges are altered, the basic clock signal being conducted via a changing number of delay units for altering the distances between the adjacent switching edges, said method comprising the step of calibrating delay times of the delay units (D 1 -Dn), wherein the delay units (D 1 -Dn) each have a plurality of delay elements ( 10 ) which are controlled to impart zero delay or a non-zero value of delay to a clock signal individually or in groups of the delay elements; wherein the respective distance between two adjacent switching edges is derived from a random number of a random number generator; and wherein the distance between two successive switching edges is derived as a function of the random number and a modulation factor.

2. The method as claimed in claim 1 , further comprising the step of calculating the position of a switching edge (a i+1 ) succeeding a switching edge (a i ) as follows:

a

i

+

1

=

(

a

i

+

p

-

(

N

-

1

2

-

Z

i

+

1

)

⁢

K

)

⁢

modp

where

p represents the number of delay steps per half-period,

N represents the number of possible switching edges,

K represents the modulation factor, and

Z represents the random number.