Granted Patent B1

US 6,920,526 · App. 09/619,771 · Granted Jul 19, 2005

Abstract

Claims (58)

1. A dual bank FIFO memory buffer, comprising:

a first bank of memory elements operable to buffer memory data;

a second bank of memory elements operable to buffer memory data;

write control address logic operable to store selected memory data in memory elements with selected addresses;

a first write pointer associated with the first bank of memory elements, the first write pointer operable to allow received data to be written to the first bank of memory elements when a second write pointer is in a null state;

a second write pointer associated with the second bank of memory elements, the second write pointer operable to allow received data to be written to the second bank of memory elements when the first write pointer is in a null state;

write control timing logic operable to selectively grant write access to the banks of memory elements at predetermined times by enabling the first and second write pointers at times dependent on received strobe signal preamble timing;

read control logic operable to read data stored in the first and second banks;

a first port connecting the dual bank FIFO memory buffer to a memory; and

a second port connecting the dual bank FIFO memory buffer to a memory controller.

2. The dual bank FIFO memory buffer of claim 1 , wherein the memory data is provided by double data rate synchronous dynamic read only memory (DDR SDRAM) operatively connected to the buffer via the first port.

3. The dual bank FIFO memory buffer of claim 1 , wherein the write control address logic is operable to determine an element within a bank of memory elements in which selected memory data is to be stored by evaluating rising and falling edges of a strobe signal.

4. The dual bank FIFO memory buffer of claim 3 , wherein the determination of the element in which selected memory data is to be stored further comprises selection of sequential element addresses during sequential strobe cycles.

5. The dual bank FIFO memory buffer of claim 1 , wherein the write control timing logic comprises a write pointer associated with each FIFO bank.

6. The dual bank FIFO memory buffer of claim 5 , wherein each write pointer is operable to control write access to its associated FIFO bank.

7. The dual bank FIFO memory buffer of claim 6 , wherein write access is granted via write pointer only during predetermined time periods when the read data is determined to be valid.

8. The dual bank FIFO memory buffer of claim 7 , wherein determination that the read data is valid comprises determination that a programmed expected time delay after issuing a read request has occurred.

9. The dual bank FIFO memory buffer of claim 8 , wherein the programmed expected time delay is determined independently for different units of memory.

10. A memory controller, comprising:

a command signal output operable to issue a data read command;

a data input operable to receive read data from a memory; and

a dual-bank FIFO connected between the data input and the memory and operable to buffer the read data, the dual-bank FIFO further comprising:

a first bank of memory elements operable to buffer memory data;

a second bank of memory elements operable to buffer memory data;

write control address logic operable to store selected memory data in memory elements with selected addresses;

a first write pointer associated with the first bank of memory elements, the first write pointer operable to allow received data to be written to the first bank of memory elements when a second write pointer is in a null state;

a second write pointer associated with the second bank of memory elements, the second write pointer operable to allow received data to be written to the second bank of memory elements when the first write pointer is in a null state;

write control timing logic operable to selectively grant write access to the banks of memory elements at predetermined times by enabling the first and second write pointers at times dependent on received strobe signal preamble timing; and

read control logic operable to read data stored in the first and second banks.

11. The memory controller of claim 10 , wherein the memory data is provided by double data rate synchronous dynamic read only memory (DDR SDRAM) operatively connected to the buffer.

12. The memory controller of claim 10 , wherein the write control address logic is operable to determine an element within a bank of memory elements in which selected memory data is to be stored by evaluating rising and falling edges of a strobe signal.

13. The memory controller of claim 12 , wherein the determination of the element in which selected memory data is to be stored further comprises selection of sequential element addresses during sequential strobe cycles.

14. The memory controller of claim 10 , wherein the write control timing logic comprises a write pointer associated with each FIFO bank.

15. The memory controller of claim 14 , wherein each write pointer is operable to control write access to its associated FIFO bank.

16. The memory controller of claim 15 , wherein write access is granted via write pointer only during predetermined time periods when the read data is determined to be valid.

17. The memory controller of claim 16 , wherein determination that the read data is valid comprises determination that a programmed expected time delay after issuing a read request has occurred.

18. A computerized information handling system, the system comprising:

a memory controller;

a memory;

a processor; and

a dual-bank FIFO connected between the memory and the memory controller and operable to buffer read data, the dual-bank FIFO further comprising:

a first bank of memory elements operable to buffer memory data;

a second bank of memory elements operable to buffer memory data;

write control address logic operable to store selected memory data in memory elements with selected addresses;

a first write pointer associated with the first bank of memory elements, the first write pointer operable to allow received data to be written to the first bank of memory elements when a second write pointer is in a null state;

a second write pointer associated with the second bank of memory elements, the second write pointer operable to allow received data to be written to the second bank of memory elements when the first write pointer is in a null state;

write control timing logic operable to selectively grant write access to the banks of memory elements at predetermined times by enabling the first and second write pointers at times dependent on received strobe signal preamble timing; and

read control logic operable to read data stored in the first and second banks.

19. The dual bank FIFO memory buffer of claim 18 , wherein the memory data is provided by double data rate synchronous dynamic read only memory (DDR SDRAM) operatively connected to the buffer.

20. The dual bank FIFO memory buffer of claim 18 , wherein the write control address logic is operable to determine an element within a bank of memory elements in which selected memory data is to be stored by evaluating rising and falling edges of a strobe signal.

21. The dual bank FIFO memory buffer of claim 20 , wherein the determination of the element in which selected memory data is to be stored further comprises selection of sequential element addresses during sequential strobe cycles.

22. The dual bank FIFO memory buffer of claim 18 , wherein the write control timing logic comprises a write pointer associated with each FIFO bank.

23. The dual bank FIFO memory buffer of claim 22 , wherein each write pointer is operable to control write access to its associated FIFO bank.

24. The dual bank FIFO memory buffer of claim 23 , wherein write access is granted via write pointer only during predetermined time periods when the read data is determined to be valid.

25. The dual bank FIFO memory buffer of claim 24 , wherein determination that the read data is valid comprises determination that a programmed expected time delay after issuing a read request has occurred.

26. The dual bank FIFO memory buffer of claim 25 , wherein the programmed expected time delay is determined independently for different units of memory.

27. A method of compensating for potential read loop delay timing-induced read errors, comprising:

selectively granting write access to a bank of FIFO buffer memory selected from a multi-bank FIFO of memory elements at determined time via write control timing logic, the write control timing logic comprising a write pointer associated with each FIFO bank and operable to control write access to the associated bank during periods when read data is determined to be valid, the multi-bank FIFO coupled between a memory and a memory controller.

Assignments (10)