Patent Assignment
Reel/Frame 035200/0722
Security Interest
Recorded: 2015-03-13
Pages: 53
Assignor
SILICON GRAPHICS INTERNATIONAL CORP.
Executed: 2015-01-27
Assignee
MORGAN STANLEY SENIOR FUNDING, INC.
1585 BROADWAY, NEW YORK, NEW YORK, 10036
Covered Properties
(473)
Method and Apparatus for Memory Access in a Matrix Processor Computer
Patent:
6,282,583 →
Application:
07/710,146 →
Method and Apparatus for User Side Scheduling in a Multiprocessor Operating System Program That Implements Distributive Scheduling of Processes
Patent:
6,195,676 →
Application:
08/003,000 →
System and Method of Addressing Distributed Memory Within a Massively Parallel Processing System
Patent:
5,765,181 →
Application:
08/165,118 →
Virtual to Logical to Physical Address Translation for Distributed Memory Massively Parallel Processing Systems
Patent:
5,784,706 →
Application:
08/165,814 →
Method for the Dynamic Allocation of Page Sizes in Virtual Memory
Patent:
5,802,341 →
Application:
08/166,451 →
Arrangement for Modifying Electrical Printed Circuit Boards
Patent:
5,834,705 →
Application:
08/205,990 →
Stream Buffers for High-Performance Computer Memory Systems
Patent:
5,761,706 →
Application:
08/333,133 →
Apparatus and Method for Testing Using Clocked Test Access Port Controller for Level Sensitive Scan Designs
Patent:
6,173,428 →
Application:
08/340,238 →
Associative Scalar Data Cache with Write-Through Capabilities for a Vector Processor
Patent:
5,717,895 →
Application:
08/348,056 →
Boundary Scan Testing Using Clocked Signal
Patent:
5,487,074 →
Application:
08/406,571 →
Adaptive Routing Mechanism for Torus Interconnection Network
Patent:
5,701,416 →
Application:
08/421,566 →
System for Randomly Modifying Virtual Channel Allocation and Accepting the Random Modification Based on the Cost Function
Patent:
5,659,796 →
Application:
08/422,072 →
Hierarchical Fat Hypercube Architecture for Parallel Processing Systems
Patent:
5,669,008 →
Application:
08/435,451 →
Programmable, Distributed Network Routing
Patent:
5,721,819 →
Application:
08/435,452 →
A System and Method for the Synchronous Transmission of Data in a Communication Network Utilizing a Source Clock Signal to Latch Serial Data into First Registers and a Handshake Signal to Latch Parallel Data into Second Registers
Patent:
5,768,529 →
Application:
08/435,453 →
Distributed Global Clock System
Patent:
5,822,381 →
Application:
08/435,455 →
System and Method for Maintaining Coherency of Virtual-to-Physical Memory Tranlations in a Multiprocessor Computer
Patent:
5,787,476 →
Application:
08/435,459 →
Directory-Based Coherence Protocol Allowing Efficient Dropping of Clean-Exclusive Data
Patent:
5,680,576 →
Application:
08/435,460 →
System and Method for Multiprocessor Partitioning to Support High Availability
Patent:
5,991,895 →
Application:
08/435,462 →
Cache Coherency Using Flexible Directory Bit Vectors
Patent:
5,634,110 →
Application:
08/435,463 →
Barrier and Eureka Synchronization Architecture for Multiprocessors
Patent:
5,721,921 →
Application:
08/450,251 →
Heatsink and Method of Forming a Heatsink
Patent:
5,829,512 →
Application:
08/520,408 →
System and Merthod for Uncached Store Buffering in a Microprocessor
Patent:
5,963,981 →
Application:
08/539,524 →
Acknowledge Triggered Forwarding of External Block Data Responses in a Microprocessor
Patent:
5,832,306 →
Application:
08/544,537 →
Virtual Maintenance Network in Multiprocessing System Having a Non- Flow Controlled Virtual Maintenance Channel
Patent:
6,055,618 →
Application:
08/550,992 →
Nigh Performance Sinusoidal Heat Sink for Heat Removal from Electronic Equipment
Patent:
5,709,263 →
Application:
08/551,070 →
Method and Apparatus for Segmenting a Database
Patent:
5,727,197 →
Application:
08/551,493 →
High Performance Spiral Heat Sink
Patent:
5,661,638 →
Application:
08/552,801 →
Readily Removable Heat Sink Assembly
Patent:
5,662,163 →
Application:
08/564,404 →
Scan Chain for Shiting the State of a Processor into Memory at a Specified Point During System Operation for Testing Purposes
Patent:
5,671,235 →
Application:
08/567,082 →
Processor-Inclusive Memory Module
Patent:
5,710,733 →
Application:
08/589,532 →
System and Method to Reduce Phase Offset and Phase Jitter in Phase-Locked and Delay-Locked Loops Using Self-Biased Circuits
Patent:
5,727,037 →
Application:
08/592,736 →
Single Connector Attachment Drive Sled Assembly Having Light Pipe Coupled to a Rail
Patent:
5,654,873 →
Application:
08/592,890 →
Transparent Relocation of Real Memory Addresses in the Main Memory of a Data Processor
Patent:
5,765,198 →
Application:
08/595,528 →
Organic Electroluminescent Device
Patent:
5,693,428 →
Application:
08/596,415 →
Daughter Card Assembly
Patent:
5,761,043 →
Application:
08/604,839 →
Air or Liquid Cooled Computer Module Cold Plate
Patent:
6,305,463 →
Application:
08/604,841 →
Cooling Approach for High Power Integrated Circuits Mounted on Printed Circuit Boards
Patent:
5,768,104 →
Application:
08/605,355 →
Bga Land Pattern
Patent:
6,091,155 →
Application:
08/606,291 →
System and Method to Reduce Jitter in Digital Delay-Locked Loops
Patent:
5,790,612 →
Application:
08/609,068 →
Procedure and System for Placement Optimization of Cells Within Circuit Blocks by Optimizing Placement of Input/Output Ports Within an Integrated Circuit Design
Patent:
5,757,658 →
Application:
08/611,785 →
Massively Parallel Processing System Using Two Data Paths: One Connecting Router Circuit to the Interconnect Network and the Other Connecting Router Circuit to I/O Controller
Patent:
5,864,738 →
Application:
08/614,859 →
System and Method for Fault-Tolerant Transmission of Data Within a Dual Ring Network
Patent:
6,233,704 →
Application:
08/614,860 →
Using External Registers to Extend Memory Reference Capabilities of a Microprocessor
Patent:
5,835,925 →
Application:
08/615,671 →
Messaging in Distributed Memory Multiprocessing System Having Shell Circuitry for Atomic Control of Message Storage Queue's Tail Pointer Structure in Local Memory
Patent:
5,841,973 →
Application:
08/615,694 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent:
5,748,900 →
Application:
08/615,700 →
Multi-Configurable Push-Pull/Open-Drain Driver Circuit
Patent:
5,811,997 →
Application:
08/638,186 →
Heat Sink with Integral Attachment Mechanism
Patent:
5,735,340 →
Application:
08/649,769 →
Raid-5 Parity Generation and Data Reconstruction
Patent:
5,805,788 →
Application:
08/650,336 →
Method and Apparatus for Adjusting the Power Supply Voltage Provided to a Microprocessor
Patent:
5,694,028 →
Application:
08/650,337 →
A System for Arbitrating Packetized Data from the Network to the Peripheral Resources and Prioritizing the Dispatching of Packets Onto the Network
Patent:
5,761,534 →
Application:
08/650,630 →
A Raid System Using I/O Buffer Segment to Temporary Store Striped and Parity Data and Connecting All Disk Drives via a Single Time Multiplexed Network
Patent:
5,862,313 →
Application:
08/650,632 →
Method and Apparatus for Removing Power-of-Two Restrictions on Distributed Addressing
Patent:
5,900,023 →
Application:
08/673,436 →
Apparatus and Method for Determining the Speed of a Semiconductor Chip
Patent:
5,818,250 →
Application:
08/675,849 →
Apparatus and Method for Dynamic Central Processing Unit Clock Adjustment
Patent:
5,774,704 →
Application:
08/688,501 →
Bulkhead Gasket Assembly
Patent:
5,770,822 →
Application:
08/697,073 →
Density Dependent Vector Mask Operation Control Apparatus and Method
Patent:
5,940,625 →
Application:
08/706,808 →
Method to Pipeline Write Misses in Shared Cache Multiprocessor Systems
Patent:
5,875,468 →
Application:
08/708,298 →
Compression Connector
Patent:
5,730,605 →
Application:
08/713,283 →
Direct Memory Access Apparatus for Transferring a Block of Data Having Discontinuous Addresses Using an Address Calculating Circuit
Patent:
6,108,722 →
Application:
08/713,602 →
Resilient Panel for Housing a Machine
Patent:
5,897,180 →
Application:
08/716,928 →
Instruction Methods for Performing Data Formatting While Moving Data Between Memory and a Vector Register File
Patent:
5,812,147 →
Application:
08/716,972 →
Packet Switched Router Architecture for Providing Multiple Simultaneous Communications
Patent:
6,683,876 →
Application:
08/717,580 →
Guaranteed Bandwidth Allocation Method in a Computer System for Input/Output Data Transfers
Patent:
5,784,569 →
Application:
08/717,581 →
Cable Management System for a Computer
Patent:
5,957,556 →
Application:
08/717,988 →
Raid System with Fibre Channel Arbitrated Loop
Patent:
5,812,754 →
Application:
08/718,743 →
Adaptive Frequency Synthesizer with Synchronization
Patent:
6,067,411 →
Application:
08/718,765 →
High Memory Capacity Dimm with Data and State Memory
Patent:
5,790,447 →
Application:
08/747,975 →
Dimm Pair with Data Memory and State Memory
Patent:
5,686,730 →
Application:
08/747,976 →
Low-Latency Real-Time Dispatching in General Purpose Multiprocessor Systems
Patent:
5,928,322 →
Application:
08/752,925 →
Apparatus and Method for Page Migration in a Non-Uniform Memory Access (Numa) System
Patent:
5,727,150 →
Application:
08/766,363 →
Guaranteeing Completion Times for Batch Jobs Without Static Partitioning
Patent:
6,353,844 →
Application:
08/773,486 →
Programmable Packer and Unpacker with Ditherer
Patent:
6,065,084 →
Application:
08/775,834 →
High Bandwidth Pci to Packet Switched Router Bridge Having Minimized Memory Latency
Patent:
5,915,104 →
Application:
08/780,781 →
Packetized Data Transmissions in a Switched Router Architecture
Patent:
6,282,195 →
Application:
08/780,785 →
Circuit for Filtering a Power Supply for Noise Sensitive Devices
Patent:
5,825,238 →
Application:
08/788,369 →
Processor-Inclusive Memory Module
Patent:
5,999,437 →
Application:
08/789,557 →
Power Switch Plunger Mechanism
Patent:
5,817,997 →
Application:
08/794,195 →
Method and System for Simultaneous High Bandwidth Input Output
Patent:
5,991,824 →
Application:
08/796,129 →
Loading and Placement Device for Connecting Circuit Boards
Patent:
5,848,906 →
Application:
08/796,302 →
Distributed Scheduling of Parallel Jobs with No Kernel-to-Kernel Communication
Patent:
6,766,515 →
Application:
08/801,646 →
System and Method for Finding Preempted Threads in a Multi-Threaded Application
Patent:
6,418,460 →
Application:
08/802,802 →
System and Method for Scheduling an Event Subject to the Availability of Requested Participants
Patent:
5,963,913 →
Application:
08/807,551 →
Rotary Latch Assembly for a Computer Housing
Patent:
5,826,922 →
Application:
08/815,636 →
Network Request Distribution Based on Static Rules and Dynamic Performance Data
Patent:
6,173,322 →
Application:
08/866,247 →
System and Method for Input/Output Flow Control in a Multiprocessor Computer System
Patent:
5,974,456 →
Application:
08/892,879 →
Processor-Inclusive Memory Module
Patent:
5,867,419 →
Application:
08/903,042 →
Method, System and Computer Program Product for Profiling Thread Virtual Memory Accesses
Patent:
5,974,536 →
Application:
08/911,192 →
Integral Actuator for a Printed Circuit Board
Patent:
5,967,825 →
Application:
08/911,909 →
Precise Detection of Errors Using Hardware Watchpoint Mechanism
Patent:
5,987,626 →
Application:
08/920,177 →
System Method and Computer Program Product for Organizing Page Caches
Patent:
6,115,790 →
Application:
08/921,257 →
Method, System, and Computer Program Product for Page Replication in a Non-Uniform Memory Access System
Patent:
6,167,437 →
Application:
08/921,545 →
Stop Align Lateral Module to Module Interconnect
Patent:
6,116,915 →
Application:
08/927,359 →
Adaptive Bandwidth Sharing
Patent:
6,205,119 →
Application:
08/931,565 →
Method, System, and Computer Program Product for Allocating Physical Memory in a Distributed Shared Memory Network
Patent:
6,249,802 →
Application:
08/933,829 →
Method, System and Computer Program Product for Managing Memory in a Non-Uniform Memory Access System
Patent:
6,289,424 →
Application:
08/933,833 →
Reverse Mapping Page Frame Data Structures to Page Table Entries.
Patent:
6,112,286 →
Application:
08/933,998 →
System, Method and Computer Program Product for Inter-Cell Page Sharing in a Distributed Shared Memory System
Patent:
6,148,379 →
Application:
08/933,999 →
Demateable, Compliant, Area Array Interconnect
Patent:
6,142,789 →
Application:
08/934,973 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent:
5,958,017 →
Application:
08/935,667 →
Method, System and Computer Program Product for Virtual Memory Support for Managing Translation Look Aside Buffers with Multiple Page Size Support
Patent:
6,112,285 →
Application:
08/935,819 →
Method, System and Computer Program Product for Dynamically Allocating Large Memory Pages of Different Sizes
Patent:
6,182,089 →
Application:
08/935,820 →
System Method and Computer Program Product for Dynamically Sizing Hash Tables
Patent:
5,960,434 →
Application:
08/938,672 →
Sliding Door Assembly for a Computer Housing
Patent:
5,924,780 →
Application:
08/940,273 →
Latching Assembly for a Computer
Patent:
5,907,962 →
Application:
08/966,611 →
Porous Metal Heat Sink
Patent:
6,018,459 →
Application:
08/971,179 →
Multiprocessor Computer System and Method for Maintaining Cache Coherence Utilizing a Multi-Demensional Cache Coherence Directory Structure
Patent:
6,633,958 →
Application:
08/971,184 →
Spacial Derivative Bus Encoder and Decoder
Patent:
6,480,548 →
Application:
08/971,185 →
Data Processing Synchronization with Automatic Queuing
Patent:
6,055,579 →
Application:
08/971,261 →
Router Table Lookup Mechanism
Patent:
5,970,232 →
Application:
08/971,587 →
Hybrid Hypercube/Torus Architecture
Patent:
6,230,252 →
Application:
08/971,588 →
Virtual Channel Assignment in Large Torus Systems
Patent:
6,101,181 →
Application:
08/971,591 →
Serialized Race-Free Virtual Barrier Network
Patent:
6,085,303 →
Application:
08/972,010 →
Improved Hot- Plug Power Supply for High- Availability Computer Systems
Patent:
6,044,424 →
Application:
08/985,562 →
Interleaving Memory in Distributed Vector Architecture Multiprocessor System
Patent:
5,913,069 →
Application:
08/987,948 →
Distributed Vector Architecture
Patent:
5,946,496 →
Application:
08/988,524 →
Message Buffering for a Computer-Based Network
Patent:
6,256,677 →
Application:
08/991,233 →
System and Method for the Direct Rendering of Curve Bounded Objects
Patent:
6,292,192 →
Application:
09/005,129 →
Modular Card Cage
Patent:
6,171,120 →
Application:
09/005,219 →
Method of Handling Arbitrary Size Message Queues in Which a Message Is Written into an Aligned Block of External Registers Within a Plurality of External Registers
Patent:
6,029,212 →
Application:
09/006,449 →
The Fabrication of Test Logic for Level Sensitive Scan on a Circuit
Patent:
6,092,226 →
Application:
09/021,651 →
Method and Apparatus for Segmenting a Database
Patent:
6,049,804 →
Application:
09/036,671 →
Diamond-Based Transformers and Power Convertors
Patent:
6,181,231 →
Application:
09/055,554 →
System and for Stacking of Integrated Circuit Packages
Patent:
6,172,874 →
Application:
09/055,677 →
Large Area, Multi-Device Heat Pipe for Stacked Mcm-Based Systems
Patent:
6,055,157 →
Application:
09/056,037 →
Quantum Acceleration of Conventional Non-Quantum Computers
Patent:
6,081,882 →
Application:
09/057,701 →
Memory System with Multiple Addressing and Control Busses
Patent:
5,870,325 →
Application:
09/060,451 →
Method and System for Efficient Context Switching in a Computer Graphics System
Patent:
6,208,361 →
Application:
09/097,601 →
Method and Apparatus for Processing a Set of Data Values with Plural Processing Units Using Mask Bits Generated by Other Processing Units
Patent:
6,308,250 →
Application:
09/103,201 →
Eigen-Mode Encoding of Signals in a Data Group
Patent:
6,226,330 →
Application:
09/118,158 →
System and Method for Maintaining Coherency of Virtual-to-Physical Memory Translations in a Multiprocessor Computer
Patent:
6,182,195 →
Application:
09/123,473 →
High Memory Capacity Dimm with Data and State Memory
Patent:
6,049,476 →
Application:
09/126,944 →
Crossbar Switch with Communication Ring Bus
Patent:
6,728,206 →
Application:
09/128,392 →
Media Coprocessor with Graphics Video and Audio Tasks Partitioned by Time Division Multiplexing
Patent:
6,275,239 →
Application:
09/137,017 →
System and Method for Fast Barrier Synchronization
Patent:
6,216,174 →
Application:
09/162,673 →
Array Address and Loop Alignment Calculations
Patent:
6,128,639 →
Application:
09/174,862 →
Advanced Firmware Boot Sequence X86 Computer System That Maintains Legacy Hardware and Software Compatibility
Patent:
6,357,003 →
Application:
09/176,694 →
Advanced Boot Sequence for an X86 Computer System That Maintains Expansion Card Device Compatibility
Patent:
6,128,731 →
Application:
09/176,696 →
Memory System with Multiple Addressing and Control Busses
Patent:
6,078,515 →
Application:
09/196,624 →
High Performance Gas Cooling System and Method
Patent:
6,167,947 →
Application:
09/215,531 →
Memory System with Switching for Data Isolation
Patent:
6,115,278 →
Application:
09/247,256 →
Method and Device for Controlling Access to Memory
Patent:
6,393,533 →
Application:
09/270,613 →
Method for Managing Concurrent Access to Virtual Memory Data Structures
Patent:
6,496,909 →
Application:
09/287,592 →
Method for Efficient Translation of Memory Addresses in Computer Systems
Patent:
6,223,270 →
Application:
09/294,830 →
Noise Estimation for Coupled Rc Interconnects in Deep Submicron Integrated Circuits
Patent:
6,732,065 →
Application:
09/301,863 →
System and Method for Providing Access to a Bus
Patent:
7,197,589 →
Application:
09/315,806 →
Memory System Including Guides That Receive Memory Modules
Patent:
6,629,855 →
Application:
09/346,638 →
Design for Circuit Board Orthogonal Installation and Removal
Patent:
6,256,196 →
Application:
09/346,659 →
Method and Apparatus for Broadcasting Invalidation Messages in a Computer System
Patent:
6,421,712 →
Application:
09/356,106 →
Door Assembly for a Computer
Patent:
6,132,019 →
Application:
09/372,660 →
Memory System with Switching for Data Isolation
Patent:
6,215,686 →
Application:
09/384,471 →
Circuit Design for High-Speed Digital Communication
Patent:
6,775,339 →
Application:
09/384,906 →
Determining a Worst Case Switching Factor for Integrated Circuit Design
Patent:
6,353,917 →
Application:
09/387,934 →
Optimizing Repeaters Positioning Along Interconnects
Patent:
6,389,581 →
Application:
09/388,938 →
Electrically Conductive Path Through a Dielectric Material
Input/Output Device Managed Timer Process
Patent:
6,594,787 →
Application:
09/399,437 →
Transfer Attribute Encoding Within Pci Constructed Address to Indicate Whether Bytes Within a Word Should Be Swapped
Patent:
6,711,636 →
Application:
09/407,421 →
Partitioning a Distributed Shared Memory Multiprocessor Computer to Facilitate Selective Hardware Maintenance
Patent:
6,516,372 →
Application:
09/407,426 →
Multiprocessor Node Controller Circuit and Method
Patent:
6,751,698 →
Application:
09/407,428 →
Translation of Pci Level Interrupts into Packet Based Messages for Edge Event Drive Microprocessors
Patent:
6,604,161 →
Application:
09/408,084 →
Computer Module Mounting System and Method
Patent:
6,452,805 →
Application:
09/408,148 →
Method and Assembly for Installation or Removal of Printed Circuit Card
Patent:
6,496,385 →
Application:
09/408,657 →
Modular Air Moving System and Method.
Patent:
6,406,257 →
Application:
09/408,769 →
System and Method for Cooling Electronicomponents
Patent:
6,366,461 →
Application:
09/408,772 →
Age-Based Network Arbitration System and Method
Patent:
6,674,720 →
Application:
09/408,778 →
Modular Computing Architecture Having Common Communication Interface
Patent:
6,829,666 →
Application:
09/408,874 →
Printed Circuit Board Carrier Insertion/Extraction Assembly
Patent:
6,193,532 →
Application:
09/408,969 →
Scalable Hypercube Multiprocessor Network for Massive Parallel Processing
Patent:
6,973,559 →
Application:
09/408,972 →
Modular Input/Output Controller Capable of Routing Packets Over Busses Operating at Different Speeds
Patent:
6,553,446 →
Application:
09/409,299 →
Diagnostic System and Method for a Highly Scalable Computing System
Patent:
6,601,183 →
Application:
09/409,438 →
System and Method for Distributing Output Queue Space
Patent:
6,532,501 →
Application:
09/409,605 →
System and Method for Memory Page Migration in a Multi-Processor Computer
Patent:
6,453,408 →
Application:
09/409,606 →
System and Method for Minimizing Error Correction Code Bits in Variable Sized Data Formats
Patent:
6,487,685 →
Application:
09/409,607 →
Method and Apparatus for Decoupling Processor Speed from Memory Subsystem Speed in a Node Controller
Patent:
6,546,451 →
Application:
09/409,639 →
Method and Apparatus for Processing Errors in a Computer System
Patent:
6,457,146 →
Application:
09/409,764 →
Method and Apparatus for Analyzing Buffer Allocation to a Device on a Peripheral Component Interconnect Bus
Patent:
6,397,274 →
Application:
09/409,765 →
Method and System for Handling Interrupts in a Node Controller Without Attached Processors
Patent:
6,564,277 →
Application:
09/409,766 →
Data Synchronizer for a Multiple Rate Clock Source and Method Thereof
Patent:
6,529,570 →
Application:
09/409,768 →
Upstream Situated Apparatus and Method for Providing High Bandwidth Data Flow Control to an Input/Output Unit
Patent:
6,622,182 →
Application:
09/409,805 →
System and Method for Shared Memory Protection in a Multiprocessor Computer
Patent:
6,381,681 →
Application:
09/410,120 →
Configurable Synchronizer for Double Data Rate Synchronous Dynamic Random Access Memory
Patent:
6,279,073 →
Application:
09/410,137 →
Method and Apparatus for Handling Invalidation Requests to Processors Not Present in a Computer System
Patent:
6,339,812 →
Application:
09/410,139 →
Method, System and Computer Program Product for Managing Memory in a Non-Uniform Memory Access System
Patent:
6,336,177 →
Application:
09/417,348 →
Multi-Processor System and Method of Accessing Data Therein
Patent:
6,651,157 →
Application:
09/418,520 →
System and Method to Provide Power to a Sea of Gates Standard Cell Block from an Overhead Bump Grid
Patent:
6,281,108 →
Application:
09/418,597 →
Abstract Verification Environment
Patent:
6,856,950 →
Application:
09/418,706 →
Exchanging Messages Between Computer Systems Communicatively Coupled in a Computer System Network
Patent:
6,766,358 →
Application:
09/427,203 →
Synchronization of Hardware Simulation Processes
Patent:
6,879,948 →
Application:
09/459,995 →
Programmable Differential Delay Circuit with Fine Delay Adjustment
Patent:
6,417,713 →
Application:
09/475,466 →
Carrier for Computer Peripheral Device
Patent:
6,381,139 →
Application:
09/475,469 →
System and Method for Adaptively Deskewing Parallel Data Signals Relative to a Clock
Patent:
7,031,420 →
Application:
09/476,678 →
Cable Dock Fixture with Emi Shielding
Patent:
6,280,257 →
Application:
09/478,968 →
High Density Computer Equipment Storage System
Patent:
6,496,366 →
Application:
09/479,824 →
Metered force single point heatsink attach mechanism
Patent:
6,169,659 →
Application:
09/498,939 →
System and Method for a Hierarchical System Management Architecture of a Highly Scalable Computing System
Patent:
6,845,410 →
Application:
09/522,695 →
Method and System for Clock Cycle Measurement and Delay Offset
Patent:
6,680,636 →
Application:
09/541,068 →
Scan Interface Chip (Sic) System and Method for Scan Testing Electronic Systems
Patent:
6,760,876 →
Application:
09/542,791 →
Housing Ground Bracket and Method
Patent:
6,574,121 →
Application:
09/548,497 →
Panel Gasket
Patent:
6,483,024 →
Application:
09/608,378 →
Electrical Connector with Latching Backplate Assembly
Patent:
6,293,813 →
Application:
09/608,935 →
System, Method and Computer Program Product for Implementing Scalable Multi-Reader/Single-Writer Locks
Patent:
6,601,120 →
Application:
09/615,312 →
Method and Apparatus for Accessing Mmr Registers Distributed Across a Large Asic
Patent:
6,779,072 →
Application:
09/619,722 →
I/O Impedance Controller
Patent:
6,703,908 →
Application:
09/619,724 →
Dual-Bank Fifo for Synchronization of Read Data in Ddr Sdram
Patent:
6,920,526 →
Application:
09/619,771 →
Baffle System for Air Cooled Computer Assembly
Patent:
6,483,699 →
Application:
09/619,818 →
Translating Write Commands to Initiate Purge Requests to Multiple Processors
Patent:
6,604,185 →
Application:
09/619,851 →
Assembly Process and Heat Sink Design for High Powerd Processor
Patent:
6,831,834 →
Application:
09/619,869 →
Discrete Delay Line System and Method
Patent:
6,518,812 →
Application:
09/619,959 →
Method and Circuit for Reliable Data Capture in the Presence of Bus-Master Changeovers
Patent:
6,839,856 →
Application:
09/620,058 →
Printed Circuit Board Component Packaging
Patent:
6,487,082 →
Application:
09/620,059 →
Variable Mode Bi-Directional and Uni-Directional Computer Communication System
Patent:
6,831,924 →
Application:
09/620,333 →
System and Method for Generating Clock Signals
Patent:
6,441,666 →
Application:
09/620,336 →
Synthesis with Automated Placement Information Feedback
Patent:
6,701,496 →
Application:
09/620,338 →
Multiprocessor System Utlizing Multiple Links to Impove Point to Point Bandwidth
Patent:
6,643,764 →
Application:
09/620,372 →
Method and Apparatus for Communicating Computer Data from One Point to Another Over a Communications Medium
Patent:
7,248,635 →
Application:
09/620,373 →
Optimize Global Net Timing with Repeater Buffers
Patent:
6,684,373 →
Application:
09/620,504 →
System and Method for Accurate Adjustment of Discrete Integrated Circuit Delay Lines
Patent:
6,496,048 →
Application:
09/620,683 →
Interface for Synchronous Data Transfer Between Domains Clocked at Different Frequencies
Patent:
7,333,516 →
Application:
09/621,315 →
Method and Apparatus for Prefetching Information and Storing the Information in a Stream Buffer
Patent:
6,901,500 →
Application:
09/627,471 →
System Method and Computer Program Product for Remote Graphics Processing
Patent:
7,274,368 →
Application:
09/629,458 →
Conditioning and filling system for a spray evaporative cooling working fluid
Patent:
6,345,515 →
Application:
09/642,957 →
System and Method for a Hierarchical System Management Architecture of a Highly Scalable Computing System
Patent:
7,219,156 →
Application:
09/644,698 →
Cache Line Converter
Patent:
6,751,705 →
Application:
09/650,101 →
Method and System for Calculating Interconnect Moments and Delay
Patent:
6,532,575 →
Application:
09/660,732 →
System for Communications Where First Priority Data Transfer Is Not Disturbed by Second Priority Data Transfer and Where Allocated Bandwidth Is Removed When Process Terminates Abnormally
Patent:
38,134 →
Application:
09/679,447 →
Method and System for Estimating Interconnect Delay
Patent:
6,853,969 →
Application:
09/713,842 →
Method and System for Determining Repeater Allocation Regions
Patent:
6,550,048 →
Application:
09/714,047 →
System and Method for Maintaining and Recovering Data Consistency Across Multiple Pages
Patent:
6,721,739 →
Application:
09/730,871 →
Computer Chassis for Dual Offset Opposing Main Boards
Maintaining Process Group Membership for Node Clusters in High Availability Computing Systems
Packetized Data Transmissions in a Switched Router Architecture
Patent:
6,985,484 →
Application:
09/896,370 →
Memory Device Storing Data and Directory Information Thereon, and Method for Providing the Directory Information and the Data in the Memory Device
System and Method for Removing Data from Processor Caches in a Distributed Multi-Processor Computer System
Patent:
8,635,410 →
Application:
09/909,700 →
System and Method for Reducing Memory Latency During Read Requests
Patent:
6,678,798 →
Application:
09/909,701 →
Queue Circuit and Method for Memory Arbitration Employing Same
Patent:
7,406,554 →
Application:
09/909,704 →
System and Method for Memory Arbitration
Patent:
6,816,947 →
Application:
09/909,705 →
Method and System for Using High Count Invalidate Acknowledgements in Distributed Shared Memory Systems
Patent:
6,718,442 →
Application:
09/910,274 →
Method and System for Storing Data at Input/Output (I/O) Interfaces for a Multiprocessor System
Patent:
6,795,900 →
Application:
09/910,363 →
Method and System for Controlling Data Access Between at Least Two Memory Arrangements
Patent:
6,839,820 →
Application:
09/910,395 →
Method and System for Maintaining Data at Input/Output (I/O) Interfaces for a Multiprocessor System
Patent:
6,981,101 →
Application:
09/910,531 →
System and Method for Transferring Ownership of Data in a Distributed Shared Memory System
Patent:
6,829,683 →
Application:
09/910,572 →
Method and System for Covering Multiple Resources with a Single Credit in a Computer System
Patent:
7,007,097 →
Application:
09/910,584 →
System and method for ordering of data transferred over multiple channels
Patent:
7,453,878 →
Application:
09/910,587 →
System and Method for Handling Updates to Memory in a Distributed Shared Memory System
Patent:
6,915,387 →
Application:
09/910,589 →
Providing Shared and Non-Shared Access to Memory in a System with Plural Processor Coherence Domains
Patent:
7,069,306 →
Application:
09/910,591 →
Method and Apparatus for Managing Node Controllers Using Partitions in a Computer System
Patent:
6,877,029 →
Application:
09/910,629 →
Method and System for Efficient Use of a Multi-Dimensional Sharing Vector in a Computer System
Patent:
6,915,388 →
Application:
09/910,630 →
Method and System for Managing Data at an Input/Output Interface for a Multiprocessor System
Patent:
6,859,863 →
Application:
09/910,631 →
Transparent Distribution and Execution of Data in a Multiprocessor Environment
Sub Rack Based Vertical Housing for Computer Systems
Remote Address Translation in a Multiprocessor System
Node Translation and Protection in a Clustered Multiprocessor System
Method and Apparatus for Handling Invalidation Requests to Processors Not Present in a Computer System
Bus Speed Controller Using Switches
Method and System for Cache Coherence in Dsm Multiprocessor System Without Growth of the Sharing Vector
System and Method for Improving Speed of Operation of Integrated Circuits
Patent:
6,621,300 →
Application:
10/131,309 →
Programmable Differential Delay Circuit with Fine Delay Adjustment
System and Method for Repairing a Memory Column
Patent:
6,724,669 →
Application:
10/142,822 →
Programmable Differential Delay Circuit with Fine Delay Adjustment
Actuatable Connector System
Clustered Filesystem
Spacial Derivative Bus Encoder and Decoder
System and Method for a Self-Calibrating Sense-Amplifier Strobe
Apparatus and Method for Maximizing Equipment Storage Density
Modular Fan Brick and Method for Exchanging Air in a Brick-Based Computer System
Method and Rack for Exchanging Air with Modular Bricks in a Computer System
Printed Circuit Board Stiffener
Backshell Assembly
Method and System for Renaming Registers in a Microprocessor
Patent:
7,406,587 →
Application:
10/210,257 →
Computer Enclosure and Method for Manufacture
Patent:
6,813,151 →
Application:
10/219,654 →
Memory Daughter Card Apparatus, Configurations, and Methods
Electromagneric Interference Cable Backshell Assembly for High-Density Interconnect
Sub Rack Based Vertical Housing for Computer Systems
System and Method for Hierarchical Approximation of Least Recently Used Replacement Algorithms Within a Cache Organized as Two or More Super-Ways of Memory Blocks
High Density Computer Equipment Storage System
System and Method for Conveying Information
Patent:
7,712,006 →
Application:
10/310,237 →
System and Method for Conveying Information
Patent:
7,447,794 →
Application:
10/310,400 →
Recovery and Relocation of a Distributed Name Service in a Cluster Filesystem
Synchronization Circuits for the Distribution of Unique Data to Scattered Locations
Global Pointers for Scalable Parallel Applications
Multi-Class Heterogeneous Clients in a Clustered Filesystem
Clustered Filesystem for Mix of Trusted and Untrusted Nodes
Messaging Between Heterogeneous Clients of a Storage Area Network
System, Method, and Computer Program Product for Applying Different Transport Mechanisms for User Interface and Image Portions of a Remotely Rendered Image
Real-Time Storage Area Network
Ventilated Housing for Electronic Components
Patent:
6,975,510 →
Application:
10/435,211 →
Computer Rack with Power Distribution System
Computer Rack Cooling System
Relocation of Metadata Server with Outstanding Dmapi Requests
Network filesystem asynchronous I/O scheduling
Method for Equitable Resource Sharing Between Local and Network Filesystems
High Density Computer Equipment Storage Systems
Patent:
6,850,408 →
Application:
10/627,375 →
Detection and Control of Resource Congestion by a Number of Processors
Address Translation Using a Page Size Tag
System and Method for Encoding Page Size Information
Sub Rack Based Vertical Housing for Computer Systems
High Density Computer Equipment Storage System
Memory Access Management in a Shared Memory Multi-Processor System
Multi-processor system and method of accessing data therein
Application:
10/696,146 →
Publication:
US 2004/0098561
Method for Retrieving and Modifying Data Elements on a Shared Medium
System and Method for Reducing Memory Latency During Read Requests
Patent:
6,938,128 →
Application:
10/725,897 →
Method and Apparatus for Maintaining Coherence Information in Multi-Cache Systems
Computer Rack Cooling System
System and Method for Performing Address Translation in a Computer System
System and Method for Performing Memory Operations in a Computing System
Patent:
7,398,359 →
Application:
10/836,932 →
Method for Performing Cache Coherency in a Computer System
Patent:
7,802,058 →
Application:
10/837,057 →
Multiprocessor Node Controller Circuit and Method
Apparatus and Method for Maximizing Equipment Storage Density
Method for Empirically Determining a Qualified Bandwidth of File Storage for a Shared Filed System
Method and System for Network Storage Device Failure Protection and Recovery
Sub Rack Based Vertical Housing for Computer Systems
Computer Rack Cooling System with Variable Airflow Impedance
Rack-Mounted Air Deflector
Computer System with Dual Operating Modes
Adaptable Power Supply
Node Synchronization for Multi-Processor Computer Systems
Anticipatory Programmable Interface Pre-Driver
Directional Fan Assembly
Electromagnetic Interference Shield for I/O Ports
Computer Rack with Cluster Modules
Interface Assembly
Rack Mounted Computer System
Fault Tolerant Memory System
Ventilated Housing for Electronic Components
Hot Plug Control Apparatus and Method
System for insertion and extraction of an electronic module
Data Coherence Method and Apparatus for Multi-Node Computer System
Power Supply Cooling System
Generation and Use of System Level Defect Tables for Main Memory
Failsoft System for Multiple Cpu System
System and Method for Reducing Back Flow
System and Method for Adaptively Deskewing Parallel Data Signals Relative to a Clock
Apparatus and Method of Controlling Data Sharing on a Shared Memory Computer System
Method and System for Managing Memory in a Multiprocessor System
Patent:
7,500,068 →
Application:
11/426,538 →
Performance Improvement for Block Span Replication
Reusing Task Object and Resources
Generating Digest for Block Range via Iscsi
Lightweight Management and High Availability Controller
Redundant Appliance Configuration Repository in Standard Hierarchical Format
Storage Resource Scan
System and Method for Optimizing Computational Density
System and Method of Synchronizing Real Time Clock Values in Arbitrary Distributed Systems
Load Balancing for Parallel Tasks
Direct Memory Access Engine for Data Transfers
High Density Computer Equipment Storage System
Flow-Through Cooling for Computer Systems
Clustered Filesystem with Membership Version Support
Clustered Filesystem with Interruptible Token Acquisition
Rack-Mounted Air Deflector
Container-Based Data Center
System, Method, and Computer Program Product for Remote Graphics Processing
High Density Computer Equipment Storage System
Non-Saturating Fairness Protocol and Method for Nacking Systems
Network Topology for a Scalable Multiprocessor System
System and Method for Performing Memory Operations in a Computing System
Patent:
7,925,839 →
Application:
12/168,689 →
Multiprocessor Node Controller Circuit and Method
System and Method for Adaptively Deskewing Parallel Data Signals Relative to a Clock
Interface Assembly
System and Method for Conveying Information
Rack Mounted Computer System Including Chassis Retainer
Hot Plug Control Apparatus and Method
Method for Empirically Determining a Qualified Bandwidth of File Storage for a Shared Filed System Using a Guaranteed Rate I/O (Grio) or Non-Grio Process
Multi-Class Heterogeneous Clients in a Clustered Filesystem
Clustered File System for Mix of Trusted and Untrusted Nodes
Interface Assembly
Method for Performing Cache Coherency in a Computer System
Clustered Filesystem with Data Volume Snapshot Maintenance
Real-Time Storage Area Network
Method for Equitable Resource Sharing Between Local and Network Filesystems
Computer System with Dual Operating Modes
System and Method for Conveying Information
Rack Mounted Computer System
System and Method for Performing Memory Operations in a Computing System
Clustered Filesystem with Membership Version Support
Relocation of Metadata Server with Outstanding Dmapi Requests
System and Method of Synchronizing Real Time Clock Values in Arbitrary Distributed Systems
Clustered Filesystems for Mix of Trusted and Untrusted Nodes
Clustered Filesystem with Data Volume Snapshot Maintenance
Detection and Control of Resource Congestion by a Number of Processors
Applying Different Transport Mechanisms for User Interface and Image Portions of a Remotely Rendered Image
System and Method for Conveying Information
System and Method for Error Logging
First-in First-Out (FIFO) Modular Memory Structure
Application:
13/784,160 →
Publication:
US 2014/0250252
High Performance System That Includes Reconfigurable Protocol Tables Within an Asic Wherein a First Protocol Block Implements an Inter-Asic Communications Protocol and a Second Block Implements an Intra-Asic Function
Multi-Class Heterogeneous Clients in a Clustered Filesystem
Global Synchronous Clock Circuit and Method for Blade Processors
Enhanced Performance Monitoring Method and Apparatus
Associative Look-up Instruction for a Processor Instruction Set Architecture
Application:
13/802,086 →
Publication:
US 2014/0281208
Apparatus and Methods for Providing Performance Data of Nodes in a High Performance Computing System
Application:
13/804,532 →
Publication:
US 2014/0280663
Maintaining Coherence When Removing Nodes From a Directory-Based Shared Memory System
Synchronizing Scheduler Interrupts Across Multiple Computing Nodes
Application:
13/828,896 →
Publication:
US 2014/0281036
Bandwidth on-Demand Adaptive Routing
Active Archive Bridge
Intelligent Front Panel
Application:
13/831,657 →
Publication:
US 2014/0281640
Dynamic Assembly and Dispatch of Controlling Software
Application:
13/831,671 →
Publication:
US 2014/0280957
Storage Zoning Tool for Assigning Data Storage Devices to a Data Storage Zone
Application:
13/831,675 →
Publication:
US 2014/0281219
Autonomous Power Sparing Storage
Application:
13/831,683 →
Publication:
US 2014/0281604
Opportunistic Tier in Hierarchical Storage
Application:
13/831,694 →
Publication:
US 2014/0281300
Temporal Hierarchical Tiered Data Storage
Application:
13/831,702 →
Publication:
US 2014/0281322
Stealth Power Management in Storage Array
Application:
13/831,719 →
Publication:
US 2014/0281621
Dynamic Storage Device Libraries
File System Replication
Application:
13/831,745 →
Publication:
US 2014/0279913
Logical Block Protection for Tape Interchange
Hierarchical System Manager Rollback
Address Resource Mapping In A Shared Memory Computer System
Elastic Hierarchical Data Storage Backend
Application:
13/835,462 →
Publication:
US 2014/0281301
Block Device Management
Fast Mount Cache
Application:
13/836,073 →
Publication:
US 2014/0281211
Data Storage Power Consumption Threshold
Application:
13/838,443 →
Publication:
US 2014/0281606
Method for Transparently Connecting Augmented Network Socket Operations
Scalable Infiniband Interconnect Performance and Diagnostic Tool
Data Coherence Method and Apparatus for Multi-Node Computer System
System, Method, and Computer Program Product for Remote Graphics Processing
Hard Disk Drive Mounting Bracket
Application:
13/853,839 →
Publication:
US 2014/0263907
Virtual Storage Pool
Micro Ethernet Connector
Pcb Mounted Cover Activated Intrusion Detection Switch
Quick Connect Coupler Rapid Disengagement Extension Mechanism
Application:
13/860,465 →
Publication:
US 2014/0265314
Network Topology for a Scalable Multiprocessor System
Tcp Server Bootloader
Application:
13/897,198 →
Publication:
US 2014/0282478
Total Quotas for Data Storage System
Allocating Accelerators to Threads in a High Performance Computing System
Application:
13/900,757 →
Publication:
US 2014/0282584
On-Blade Cold Sink For High-Density Clustered Computer System
Twin Server Blades for High-Density Clustered Computer System
Closed-Loop Cooling System for High-Density Clustered Computer System
System for Cooling Multiple in-Line Central Processing Units in a Confined Enclosure
Application:
13/931,781 →
Publication:
US 2014/0268553
External Access of Internal Sas Topology in Storage Server
Application:
13/931,782 →
Publication:
US 2014/0281094
High-Density Multidirectional Midplane Having a Plurality of Pins
Application:
13/931,784 →
Publication:
US 2014/0273556
Combining Parallel Coordinates and Histograms
Application:
13/931,785 →
Publication:
US 2015/0007079
Interactive Alignment of Graph Axes
Application:
13/931,788 →
Publication:
US 2015/0007111
Replicated Database Using One Sided Rdma
Application:
13/931,790 →
Publication:
US 2015/0006478
High Speed Disk Array Spider Cable
Application:
13/931,793 →
Publication:
US 2014/0281105
Jbod Cable
Application:
13/931,796 →
Publication:
US 2014/0268538
Volume Rendering for Graph Renderization
Application:
13/931,797 →
Publication:
US 2015/0007113
Rotation and Translation of Graphical Scenes Using Virtual Track Ball
Application:
13/931,806 →
Publication:
US 2015/0007087
Server with Heat Pipe Cooling
Server with Heat Baffle Cooling
Application:
13/931,814 →
Publication:
US 2014/0268552
Toolless Hot Swappable Storage Module
Integrated Visualization
Dynamic Resource Scheduling
Localized Fast Bulk Storage in a Multi-Node Computer System
Populating Localized Fast Bulk Storage in a Multi-Node Computer System
Independent Removable Computer Rack Power Distribution System for High-Density Clustered Computer System
Transactional Memory Proxy
Enclosure High Pressure Push-Pull Airflow
Application:
14/038,588 →
Publication:
US 2014/0268551
Scalable Matrix Multiplication in a Shared Memory System
Application:
14/041,974 →
Publication:
US 2014/0331014
Clustered Filesystems for Mix of Trusted and Untrusted Nodes
System, Method, and Computer Program Product for Remote Graphics Processing
Real-Time Storage Area Network
Rotation of Graphical Scenes
Application:
14/042,723 →
Publication:
US 2015/0007096
Bidirectional Slide Rail
Application:
14/082,090 →
Publication:
US 2014/0265793
Network Filesystem Asynchronous I/O Scheduling
System and Method for Removing Data from Processor Caches in a Distributed Multi-Processor Computer System
Clustered Filesystem with Membership Version Support
Software Design Pattern for Adapting a Graph Database Visualization Software
Application:
14/266,656 →
Publication:
US 2014/0330867
Deploying Software in a Multi-Instance Node
Platform and Software Framework for Data Intensive Applications in the Cloud
Pressure-Activated Server Cooling System
Application:
14/289,590 →
Publication:
US 2015/0003010
System, Method, and Computer Program Product for Remote Graphics Processing
Multi-Class Heterogeneous Clients in a Clustered Filesystem
Radial Computer System
Patent:
436,950 →
Application:
29/113,555 →
Computer Chassis for Dual, Opposing Main Boards
Patent:
475,705 →
Application:
29/118,970 →
Drive sled handle
Patent:
444,471 →
Application:
29/125,872 →
Drive sled cover
Patent:
444,474 →
Application:
29/125,873 →
Front panel media door
Patent:
445,425 →
Application:
29/125,876 →
Server door
Patent:
445,112 →
Application:
29/127,551 →
Server cover
Patent:
444,461 →
Application:
29/127,590 →
Panel
Patent:
464,973 →
Application:
29/135,733 →
Panel
Patent:
464,054 →
Application:
29/135,803 →
Industrial Rack
Patent:
463,796 →
Application:
29/136,032 →
Portion of a Bank of Computer Chassis Mounted to Rack Bars
Patent:
473,225 →
Application:
29/137,456 →
Server Product Faceplate
Patent:
464,056 →
Application:
29/146,729 →
Set of Multi Device Faceplates
Patent:
473,561 →
Application:
29/148,943 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 18, 2014
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 032714/0032 →
Merger
Apr 18, 2014
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 032714/0427 →
Change of Name
Apr 18, 2014
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 032714/0230 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests...
Apr 24, 2014
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0001 →
Merger
Apr 24, 2014
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 032758/0516 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests...
Apr 24, 2014
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0847 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests...
Apr 24, 2014
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0467 →
Assignment of Assignor's Interest
Apr 24, 2014
From: SPIX, GEORGE A.; WENGELSKI, DIANE M.; HAWKINSON, STUART W.; JOHNSON, MARK D.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 032752/0532 →
Release of Security Interest
Apr 25, 2014
From: IBM HOLDINGS, INC.
To: CRAY RESEARCH, INC. C/O DAVID E. FRASCH
Reel/Frame 032757/0428 →
Assignment of Assignor's Interest
Apr 25, 2014
From: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
To: IBM HOLDINGS, INC.
Reel/Frame 032757/0293 →
Assignment of Assignor's Interest
Jan 22, 2015
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 034804/0446 →
Merger
Jan 22, 2015
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 034804/0437 →
Change of Name
Jan 22, 2015
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 034804/0661 →
Merger
Jan 28, 2015
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 034837/0218 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests.
Jul 25, 2016
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 039461/0522 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests. . .
Jul 25, 2016
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS INC
Reel/Frame 039461/0765 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests.
Jul 25, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039461/0713 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests.
Jul 26, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039482/0015 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests.
Jul 26, 2016
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 039474/0606 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests
Jul 27, 2016
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC
Reel/Frame 039484/0869 →
Change of Name
Aug 9, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 039636/0809 →
Assignment of Assignor's Interest
Oct 21, 2016
From: CRAY RESEARCH, L.L.C.
To: SILICON GRAPHICS, INC.
Reel/Frame 040092/0651 →
Merger
Oct 21, 2016
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 040464/0893 →
Release of Security Interest
Nov 2, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS AGENT
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040545/0362 →
Assignment of Assignor's Interest
Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →