System and method for performing memory operations in a computing system
View Patent ↗A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
1. A method for performing memory operations in a computing system, comprising:
transitioning a cache line associated with a memory location from a conventional MESI coherency protocol to one of a plurality of transactional coherency states associated with a Transaction operating state of a processor;
performing updates to the cache line associated with the memory location, the updates to the cache line not being visible to other processors in the computing system;
identifying the cache line with a transaction coherency state according to the update performed.
2. The method of claim 1 , further comprising:
receiving a commit instruction;
transitioning to a Commit operating state;
making any changes to the cache line visible to other processors in the computing system.
3. The method of claim 2 , further comprising:
transitioning the cache line from one of the plurality of transactional states to the conventional MESI protocol;
transitioning to a Normal operating state upon making changes to the cache line visible to other processors and performing the cache line transition.
4. The method of claim 1 , further comprising:
receiving an event causing an abort of the cache line update;
transitioning to an Abort operating state in response to the event.
5. The method of claim 4 , further comprising:
discarding any changes made to the cache line;
transitioning the cache line associated with the memory location from one of a plurality of transactional coherency states associated with the Transaction operating state to the conventional MESI coherency protocol.
6. The method of claim 5 , further comprising:
transitioning to a Suspended operating state upon completion of the discarding of any changes to the cache line.
7. The method of claim 1 , further comprising:
processing MESI coherency protocol messages received from other processors.
8. The method of claim 1 , further comprising:
tracking a state of the processor and operations performed on the cache line.
9. A computer readable storage medium including code for performing memory operations in a computing system, the code operable to:
transition a cache line associated with a memory location from a conventional MESI coherency protocol to one of a plurality of transactional coherency states associated with a Transaction operating state of a processor;
perform updates to the cache line associated with the memory location, the updates to the cache line not being visible to other processors in the computing system;
identify the cache line with a transaction coherency state according to the update performed.
10. The computer readable medium of claim 9 , wherein the code is further operable to:
receive a commit instruction;
transition to a Commit operating state;
make any changes to the cache line visible to other processors in the computing system.
11. The computer readable medium of claim 10 , wherein the code is further operable to:
transition the cache line from one of the plurality of transactional states to the conventional MESI protocol;
transition to a Normal operating state upon making changes to the cache line visible to other processors and performing the cache line transition.
12. The computer readable medium of claim 9 , wherein the code is further operable to:
receive an event causing an abort of the cache line update;
transition to an Abort operating state in response to the event.
13. The computer readable medium of claim 12 , wherein the code is further operable to:
discard any changes made to the cache line;
transition the cache line associated with the memory location from one of a plurality of transactional coherency states associated with the Transaction operating state to the conventional MESI coherency protocol.
14. The computer readable medium of claim 9 , wherein the code is further operable to:
process MESI coherency protocol messages received from other processors.
15. The computer readable medium of claim 14 , wherein processing of MESI coherency protocol messages causes updates to the cache line to be aborted.
16. A system for performing memory operations in a computing system, comprising:
means for transitioning a cache line associated with a memory location from a conventional MESI coherency protocol to one of a plurality of transactional coherency states associated with a Transaction operating state of a processor;
means for performing updates to the cache line associated with the memory location, the updates to the cache line not being visible to other processors in the computing system;
means for identifying the cache line with a transaction coherency state according to the update performed.
17. The system of claim 16 , further comprising:
means for transitioning to a Commit operating state;
means for making any changes to the cache line visible to other processors in the computing system.
18. The system of claim 17 , further comprising:
means for transitioning the cache line from one of the plurality of transactional states to the conventional MESI protocol;
means for transitioning to a Normal operating state upon making changes to the cache line visible to other processors and performing the cache line transition.
19. The system of claim 16 , further comprising:
means for receiving an event causing an abort of the cache line update;
means for transitioning to an Abort operating state in response to the event.
20. The system of claim 19 , further comprising:
means for discarding any changes made to the cache line;
means for transitioning the cache line associated with the memory location from one of a plurality of transactional coherency states associated with the Transaction operating state to the conventional MESI coherency protocol.
21. The computer readable medium of claim 16 , wherein the code is further operable to:
process MESI coherency protocol messages received from other processors.
22. The computer readable medium of claim 21 , wherein processing of MESI coherency protocol messages causes updates to the cache line to be aborted.