Granted Patent B2

US 7,181,589 · App. 10/835,855 · Granted Feb 20, 2007

Abstract

Claims (52)

1. A method for performing address translation in a computer system, comprising:

identifying a base virtual address and a block size for a block of memory;

adding the block size to the base virtual address to establish an end virtual address for the block of memory;

receiving an input virtual address to a location in the memory;

determining whether the input virtual address is within a range defined by the base virtual address and the end virtual address;

generating an index to a physical base address in a physical base table in response to the virtual address being within the range, the index being generated by:

subtracting the base virtual address from the input virtual address to obtain a first index result;

subtracting a node block size from the first result to obtain a second index result;

identifying particular bits in the second result to obtain the index;

generating an offset, the offset being generated by:

subtracting the base virtual address from the input virtual address to obtain a first offset result;

dividing the first offset result by the node block size to obtain the offset;

generating a physical address in response to the offset and the physical base address, the physical address being the physical base address plus the offset.

2. The method of claim 1 , further comprising:

generating the physical address from the virtual address through a translation lookaside buffer in response to the virtual address not being within the range.

3. The method of claim 1 , further comprising: repeating the determination of whether the virtual address is within the range for each entry of the physical base table.

4. The method of claim 1 , further comprising:

generating a hit indication in response to the virtual address being in the range.

5. The method of claim 1 , further comprising:

generating a miss indication in response to the virtual address not being in the range.

6. The method of claim 1 , further comprising:

providing access to the location in memory in accordance with the physical address.

7. A system for performing address translation in a computer system, comprising:

a processor operable to generate a virtual address to a memory location;

an address translator operable to generate a physical address in response to the virtual address, the address translator operable to generate the virtual address using a translation buffer in response to the virtual address not being in a predetermined range, the address translator operable to generate the physical address using a segmentation buffer in response to the virtual address being in the range, wherein the address translator implements the method of claim 1 ;

a memory operable to access the memory location from the physical address.

8. The system of claim 7 , wherein the segmentation buffer includes a plurality of entries each having a base virtual address field, a total block size field, a node block size field, a physical base table, a shift field, and an attribute field.

9. The system of claim 8 , wherein the address translator compares the virtual address to the range defined by the base virtual address field and the total block size field.

10. The system of claim 9 , wherein the address translator generates a miss indication in response to the virtual address not being in the range of any entry of the segmentation buffer.

11. The system of claim 9 , wherein the address translator generates a hit indication in response to the virtual address being within the range of any entry of the segmentation buffer.

12. The system of claim 7 , wherein the processor is given access to the memory location identified by the physical address.

13. A system for performing address translation in a computer system, comprising:

means for identifying a base virtual address and a block size for a block of memory;

means for adding the block size to the base virtual address to establish an end virtual address for the block of memory;

means for receiving an input virtual address to a location in the memory;

means for determining whether the input virtual address is within a range defined by the base virtual address and the end virtual address;

means for generating an index to a physical base address in a physical base table in response to the virtual address being within the range, the means for generating the index including:

means for subtracting the base virtual address from the input virtual address to obtain a first index result;

means for subtracting a node block size from the first result to obtain a second index result;

means for identifying particular bits in the second result to obtain the index;

means for generating an offset, the means for generating the offset including:

means for subtracting the base virtual address from the input virtual address to obtain a first offset result;

means for dividing the first offset result by the node block size to obtain the offset;

means for generating a physical address in response to the offset and the physical base address, the physical address being the physical base address plus the offset.

14. The system of claim 13 , further comprising:

means for repeating the determination of whether the virtual address is within the range for each entry of the physical base table.

15. The system of claim 13 , further comprising:

means for generating a hit indication in response to the virtual address being in the range.

16. The system of claim 13 , further comprising:

means for generating a miss indication in response to the virtual address not being in the range.

17. The system of claim 13 , further comprising:

means for providing access to the location in memory in accordance with the physical address.

Assignments (9)