Method and system for controlling data access between at least two memory arrangements
View Patent ↗A method and system for controlling an access to a first memory arrangement and a second memory arrangement. The method and system are adapted for controlling access to the first memory arrangement and to the second memory arrangement. A token is passed from a device associated with the first memory arrangement if the access to at least one portion of the first memory arrangement is completed, and the access to the portion of the memory arrangement is disabled. Then, upon a receipt of the token, the access to at least one portion of the second memory arrangement is enabled.
1. A method for controlling access to a first memory arrangement and a second memory arrangement, comprising the steps of:
passing a token if access to at least one portion of the first memory arrangement is completed;
after the passing step, disabling the access to the at least one portion of the first memory arrangement; and
upon a receipt of the token, enabling access to at least one portion of the second memory arrangement.
2. The method according to claim 1 , wherein the passing and enabling steps are performed during a predetermined time period.
3. The method according to claim 2 , wherein the predetermined time period is a single clock period.
4. The method according to claim 1 , wherein the first memory arrangement includes a left side and a right side, and wherein the second memory arrangement includes a left side and a right side.
5. The method according to claim 4 , wherein the disabling step is performed by disabling the access to the left side of the first memory arrangement, and wherein the enabling step is performed by enabling the access to the left side of the second memory arrangement.
6. The method according to claim 4 , wherein the disabling step is performed by disabling the access to the right side of the first memory arrangement, and wherein the enabling step is performed by enabling access to the right side of the second memory arrangement.
7. The method according to claim 1 , wherein the passing step comprises sending the token by a first controller to a second controller, the first controller controlling the access to the first memory arrangement, the second controller controlling the access to the second memory arrangement.
8. The method according to claim 7 , wherein the first controller disables the access to the at least one portion of the first memory arrangement, and the second controller enables the access to the at least one portion of the second memory arrangement.
9. The method according to claim 7 , further comprising the steps of:
if the access to the at least one portion of the second memory arrangement is completed, passing the token by the second controller;
after the token is passed by the first controller sending step, disabling the access to the at least one portion of the second memory arrangement by the second controller; and
upon a receipt of the token at the first controller, enabling the access to the at least one portion of the first memory arrangement.
10. The method according to claim 1 , wherein the access includes a write operation.
11. The method according to claim 1 , wherein the access includes a read operation.
12. The method according to claim 1 , further comprising the steps of:
receiving a further token from an arbitration queue; and
utilizing the further token to perform at least one of the following operations:
accelerating a transfer of data to the first memory arrangement, and
determining if gaps exist in the data.
13. A system for controlling access to a first memory arrangement and a second memory arrangement, comprising:
a first controller controlling access to at least one portion of the first memory arrangement; and
a second controller controlling access to at least one portion of the second memory arrangement,
wherein the first controller passes a token to the second controller if the access to the at least one portion of the first memory arrangement is completed, and disables the access to the at least one portion of the first memory arrangement, and
wherein, upon a receipt of the token, the second controller enables the access to the at least one portion of the second memory arrangement.
14. The system according to claim 13 , wherein the first controller passes the token, and enables the access to the at least one portion of the first memory arrangement during a predetermined time period.
15. The system according to claim 14 , wherein the predetermined time period is a single clock period.
16. The system according to claim 13 , wherein the first memory arrangement includes a left side and a right side, and wherein the second memory arrangement includes a left side and a right side.
17. The system according to claim 16 , wherein the first controller disables the access to the at least one portion of the first memory arrangement by disabling the access to the left side of the first memory arrangement, and wherein the second controller enables the access to the at least one portion of the second memory arrangement by enabling the access to the left side of the second memory arrangement.
18. The system according to claim 16 , wherein the first controller disables the access to the at least one portion of the first memory arrangement by disabling the access to the right side of the first memory arrangement, and wherein the second controller enables the access to the at least one portion of the second memory arrangement by enabling the access to the right side of the second arrangement.
19. The system according to claim 13 , wherein, if the access to the at least one portion of the second memory arrangement is completed, the second controller passes the token from the second controller to the first controller, and disables the access to the at least one portion of the second memory arrangement, and
wherein the first controller enables the access to the at least one portion of the second memory arrangement upon a receipt of the token from the second controller.
20. The system according to claim 13 , wherein the access includes a write operation.
21. The system according to claim 13 , wherein the access includes a read operation.
22. The system according to claim 1 , further comprising:
a third controller receiving a further token from an arbitration queue, and utilizing the further token to perform at least one of the following operations:
accelerating a transfer of data to the first memory arrangement, and
determining if gaps exist in the data.