IP Library › Assignment 032714/0427
Patent Assignment
Reel/Frame 032714/0427

Merger

Recorded: 2014-04-18 Pages: 9
Assignor
SGI INTERNATIONAL, INC.
Executed: 2012-08-08
Assignee
SILICON GRAPHICS INTERNATIONAL CORP.
900 N. MCCARTHY BOULEVARD, MILPITAS, CALIFORNIA, 95035
Covered Properties (139)
Method and Apparatus for Memory Access in a Matrix Processor Computer
Patent: 6,282,583 →
Application: 07/710,146 →
System and Method for Piggybacking of Read Responses on a Shared Memory Multiprocessor Bus
Patent: 5,655,102 →
Application: 08/128,081 →
System and Method of Addressing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,765,181 →
Application: 08/165,118 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 5,696,922 →
Application: 08/165,388 →
Virtual to Logical to Physical Address Translation for Distributed Memory Massively Parallel Processing Systems
Patent: 5,784,706 →
Application: 08/165,814 →
Method for the Dynamic Allocation of Page Sizes in Virtual Memory
Patent: 5,802,341 →
Application: 08/166,451 →
Disk Drive Bracket
Patent: 5,564,804 →
Application: 08/168,166 →
Arrangement for Modifying Electrical Printed Circuit Boards
Patent: 5,834,705 →
Application: 08/205,990 →
Stream Buffers for High-Performance Computer Memory Systems
Patent: 5,761,706 →
Application: 08/333,133 →
Apparatus and Method for Testing Using Clocked Test Access Port Controller for Level Sensitive Scan Designs
Patent: 6,173,428 →
Application: 08/340,238 →
Associative Scalar Data Cache with Write-Through Capabilities for a Vector Processor
Patent: 5,717,895 →
Application: 08/348,056 →
Boundary Scan Testing Using Clocked Signal
Patent: 5,487,074 →
Application: 08/406,571 →
Adaptive Routing Mechanism for Torus Interconnection Network
Patent: 5,701,416 →
Application: 08/421,566 →
System for Randomly Modifying Virtual Channel Allocation and Accepting the Random Modification Based on the Cost Function
Patent: 5,659,796 →
Application: 08/422,072 →
Hierarchical Fat Hypercube Architecture for Parallel Processing Systems
Patent: 5,669,008 →
Application: 08/435,451 →
Programmable, Distributed Network Routing
Patent: 5,721,819 →
Application: 08/435,452 →
A System and Method for the Synchronous Transmission of Data in a Communication Network Utilizing a Source Clock Signal to Latch Serial Data into First Registers and a Handshake Signal to Latch Parallel Data into Second Registers
Patent: 5,768,529 →
Application: 08/435,453 →
Distributed Global Clock System
Patent: 5,822,381 →
Application: 08/435,455 →
Directory-Based Coherence Protocol Allowing Efficient Dropping of Clean-Exclusive Data
Patent: 5,680,576 →
Application: 08/435,460 →
System and Method for Multiprocessor Partitioning to Support High Availability
Patent: 5,991,895 →
Application: 08/435,462 →
Cache Coherency Using Flexible Directory Bit Vectors
Patent: 5,634,110 →
Application: 08/435,463 →
Barrier and Eureka Synchronization Architecture for Multiprocessors
Patent: 5,721,921 →
Application: 08/450,251 →
Heatsink and Method of Forming a Heatsink
Patent: 5,829,512 →
Application: 08/520,408 →
System and Merthod for Uncached Store Buffering in a Microprocessor
Patent: 5,963,981 →
Application: 08/539,524 →
Acknowledge Triggered Forwarding of External Block Data Responses in a Microprocessor
Patent: 5,832,306 →
Application: 08/544,537 →
Virtual Maintenance Network in Multiprocessing System Having a Non- Flow Controlled Virtual Maintenance Channel
Patent: 6,055,618 →
Application: 08/550,992 →
Nigh Performance Sinusoidal Heat Sink for Heat Removal from Electronic Equipment
Patent: 5,709,263 →
Application: 08/551,070 →
High Performance Spiral Heat Sink
Patent: 5,661,638 →
Application: 08/552,801 →
Readily Removable Heat Sink Assembly
Patent: 5,662,163 →
Application: 08/564,404 →
Scan Chain for Shiting the State of a Processor into Memory at a Specified Point During System Operation for Testing Purposes
Patent: 5,671,235 →
Application: 08/567,082 →
Processor-Inclusive Memory Module
Patent: 5,710,733 →
Application: 08/589,532 →
System and Method to Reduce Phase Offset and Phase Jitter in Phase-Locked and Delay-Locked Loops Using Self-Biased Circuits
Patent: 5,727,037 →
Application: 08/592,736 →
Single Connector Attachment Drive Sled Assembly Having Light Pipe Coupled to a Rail
Patent: 5,654,873 →
Application: 08/592,890 →
Transparent Relocation of Real Memory Addresses in the Main Memory of a Data Processor
Patent: 5,765,198 →
Application: 08/595,528 →
Daughter Card Assembly
Patent: 5,761,043 →
Application: 08/604,839 →
Air or Liquid Cooled Computer Module Cold Plate
Patent: 6,305,463 →
Application: 08/604,841 →
Cooling Approach for High Power Integrated Circuits Mounted on Printed Circuit Boards
Patent: 5,768,104 →
Application: 08/605,355 →
Bga Land Pattern
Patent: 6,091,155 →
Application: 08/606,291 →
System and Method to Reduce Jitter in Digital Delay-Locked Loops
Patent: 5,790,612 →
Application: 08/609,068 →
Procedure and System for Placement Optimization of Cells Within Circuit Blocks by Optimizing Placement of Input/Output Ports Within an Integrated Circuit Design
Patent: 5,757,658 →
Application: 08/611,785 →
Massively Parallel Processing System Using Two Data Paths: One Connecting Router Circuit to the Interconnect Network and the Other Connecting Router Circuit to I/O Controller
Patent: 5,864,738 →
Application: 08/614,859 →
System and Method for Fault-Tolerant Transmission of Data Within a Dual Ring Network
Patent: 6,233,704 →
Application: 08/614,860 →
Using External Registers to Extend Memory Reference Capabilities of a Microprocessor
Patent: 5,835,925 →
Application: 08/615,671 →
Messaging in Distributed Memory Multiprocessing System Having Shell Circuitry for Atomic Control of Message Storage Queue's Tail Pointer Structure in Local Memory
Patent: 5,841,973 →
Application: 08/615,694 →
Multi-Configurable Push-Pull/Open-Drain Driver Circuit
Patent: 5,811,997 →
Application: 08/638,186 →
Packet Switched Router Architecture for Providing Multiple Simultaneous Communications
Patent: 6,683,876 →
Application: 08/717,580 →
System and Method for Scheduling an Event Subject to the Availability of Requested Participants
Patent: 5,963,913 →
Application: 08/807,551 →
Network Request Distribution Based on Static Rules and Dynamic Performance Data
Patent: 6,173,322 →
Application: 08/866,247 →
Method, System and Computer Program Product for Profiling Thread Virtual Memory Accesses
Patent: 5,974,536 →
Application: 08/911,192 →
System Method and Computer Program Product for Organizing Page Caches
Patent: 6,115,790 →
Application: 08/921,257 →
Method, System, and Computer Program Product for Page Replication in a Non-Uniform Memory Access System
Patent: 6,167,437 →
Application: 08/921,545 →
Method, System, and Computer Program Product for Allocating Physical Memory in a Distributed Shared Memory Network
Patent: 6,249,802 →
Application: 08/933,829 →
Reverse Mapping Page Frame Data Structures to Page Table Entries.
Patent: 6,112,286 →
Application: 08/933,998 →
System, Method and Computer Program Product for Inter-Cell Page Sharing in a Distributed Shared Memory System
Patent: 6,148,379 →
Application: 08/933,999 →
Method, System and Computer Program Product for Virtual Memory Support for Managing Translation Look Aside Buffers with Multiple Page Size Support
Patent: 6,112,285 →
Application: 08/935,819 →
Method, System and Computer Program Product for Dynamically Allocating Large Memory Pages of Different Sizes
Patent: 6,182,089 →
Application: 08/935,820 →
System Method and Computer Program Product for Dynamically Sizing Hash Tables
Patent: 5,960,434 →
Application: 08/938,672 →
Multiprocessor Computer System and Method for Maintaining Cache Coherence Utilizing a Multi-Demensional Cache Coherence Directory Structure
Patent: 6,633,958 →
Application: 08/971,184 →
Router Table Lookup Mechanism
Patent: 5,970,232 →
Application: 08/971,587 →
Virtual Channel Assignment in Large Torus Systems
Patent: 6,101,181 →
Application: 08/971,591 →
Distributed Vector Architecture
Patent: 5,946,496 →
Application: 08/988,524 →
Crossbar Switch with Communication Ring Bus
Patent: 6,728,206 →
Application: 09/128,392 →
Method and Device for Controlling Access to Memory
Patent: 6,393,533 →
Application: 09/270,613 →
System and Method for Providing Access to a Bus
Patent: 7,197,589 →
Application: 09/315,806 →
Memory System Including Guides That Receive Memory Modules
Patent: 6,629,855 →
Application: 09/346,638 →
Method and Apparatus for Broadcasting Invalidation Messages in a Computer System
Patent: 6,421,712 →
Application: 09/356,106 →
Input/Output Device Managed Timer Process
Patent: 6,594,787 →
Application: 09/399,437 →
System and Method for Distributing Output Queue Space
Patent: 6,532,501 →
Application: 09/409,605 →
System and Method for Memory Page Migration in a Multi-Processor Computer
Patent: 6,453,408 →
Application: 09/409,606 →
System and Method for Minimizing Error Correction Code Bits in Variable Sized Data Formats
Patent: 6,487,685 →
Application: 09/409,607 →
Method and Apparatus for Decoupling Processor Speed from Memory Subsystem Speed in a Node Controller
Patent: 6,546,451 →
Application: 09/409,639 →
Method and Apparatus for Processing Errors in a Computer System
Patent: 6,457,146 →
Application: 09/409,764 →
Method and Apparatus for Analyzing Buffer Allocation to a Device on a Peripheral Component Interconnect Bus
Patent: 6,397,274 →
Application: 09/409,765 →
Method and System for Handling Interrupts in a Node Controller Without Attached Processors
Patent: 6,564,277 →
Application: 09/409,766 →
Data Synchronizer for a Multiple Rate Clock Source and Method Thereof
Patent: 6,529,570 →
Application: 09/409,768 →
Upstream Situated Apparatus and Method for Providing High Bandwidth Data Flow Control to an Input/Output Unit
Patent: 6,622,182 →
Application: 09/409,805 →
Configurable Synchronizer for Double Data Rate Synchronous Dynamic Random Access Memory
Patent: 6,279,073 →
Application: 09/410,137 →
System and Method to Provide Power to a Sea of Gates Standard Cell Block from an Overhead Bump Grid
Patent: 6,281,108 →
Application: 09/418,597 →
Exchanging Messages Between Computer Systems Communicatively Coupled in a Computer System Network
Patent: 6,766,358 →
Application: 09/427,203 →
Synchronization of Hardware Simulation Processes
Patent: 6,879,948 →
Application: 09/459,995 →
Electrical Connector with Latching Backplate Assembly
Patent: 6,293,813 →
Application: 09/608,935 →
System, Method and Computer Program Product for Implementing Scalable Multi-Reader/Single-Writer Locks
Patent: 6,601,120 →
Application: 09/615,312 →
Method and System for Calculating Interconnect Moments and Delay
Patent: 6,532,575 →
Application: 09/660,732 →
Method and System for Estimating Interconnect Delay
Patent: 6,853,969 →
Application: 09/713,842 →
Method and System for Determining Repeater Allocation Regions
Patent: 6,550,048 →
Application: 09/714,047 →
System and Method for Maintaining and Recovering Data Consistency Across Multiple Pages
Patent: 6,721,739 →
Application: 09/730,871 →
Maintaining Process Group Membership for Node Clusters in High Availability Computing Systems
Patent: 7,627,694 →
Application: 09/811,158 →
Publication: US 2002/0049845
Memory Device Storing Data and Directory Information Thereon, and Method for Providing the Directory Information and the Data in the Memory Device
Patent: 6,775,742 →
Application: 09/909,693 →
Publication: US 2002/0032838
Queue Circuit and Method for Memory Arbitration Employing Same
Patent: 7,406,554 →
Application: 09/909,704 →
System and Method for Memory Arbitration
Patent: 6,816,947 →
Application: 09/909,705 →
Method and System for Using High Count Invalidate Acknowledgements in Distributed Shared Memory Systems
Patent: 6,718,442 →
Application: 09/910,274 →
Method and System for Storing Data at Input/Output (I/O) Interfaces for a Multiprocessor System
Patent: 6,795,900 →
Application: 09/910,363 →
Method and System for Controlling Data Access Between at Least Two Memory Arrangements
Patent: 6,839,820 →
Application: 09/910,395 →
Method and System for Maintaining Data at Input/Output (I/O) Interfaces for a Multiprocessor System
Patent: 6,981,101 →
Application: 09/910,531 →
System and Method for Transferring Ownership of Data in a Distributed Shared Memory System
Patent: 6,829,683 →
Application: 09/910,572 →
Method and System for Covering Multiple Resources with a Single Credit in a Computer System
Patent: 7,007,097 →
Application: 09/910,584 →
System and Method for Handling Updates to Memory in a Distributed Shared Memory System
Patent: 6,915,387 →
Application: 09/910,589 →
Method and Apparatus for Managing Node Controllers Using Partitions in a Computer System
Patent: 6,877,029 →
Application: 09/910,629 →
Method and System for Efficient Use of a Multi-Dimensional Sharing Vector in a Computer System
Patent: 6,915,388 →
Application: 09/910,630 →
Method and System for Managing Data at an Input/Output Interface for a Multiprocessor System
Patent: 6,859,863 →
Application: 09/910,631 →
Transparent Distribution and Execution of Data in a Multiprocessor Environment
Patent: 7,249,357 →
Application: 09/934,443 →
Publication: US 2003/0036809
Remote Address Translation in a Multiprocessor System
Patent: 6,925,547 →
Application: 10/017,488 →
Publication: US 2002/0169938
Node Translation and Protection in a Clustered Multiprocessor System
Patent: 7,356,026 →
Application: 10/020,854 →
Publication: US 2002/0172199
Bus Speed Controller Using Switches
Patent: 6,799,238 →
Application: 10/068,991 →
Publication: US 2003/0149805
Method and System for Cache Coherence in Dsm Multiprocessor System Without Growth of the Sharing Vector
Patent: 6,877,030 →
Application: 10/084,088 →
Publication: US 2003/0163543
System and Method for Improving Speed of Operation of Integrated Circuits
Patent: 6,621,300 →
Application: 10/131,309 →
System and Method for Repairing a Memory Column
Patent: 6,724,669 →
Application: 10/142,822 →
Actuatable Connector System
Patent: 6,672,878 →
Application: 10/160,437 →
Publication: US 2003/0224630
System and Method for a Self-Calibrating Sense-Amplifier Strobe
Patent: 6,714,464 →
Application: 10/180,478 →
Publication: US 2004/0001364
Modular Fan Brick and Method for Exchanging Air in a Brick-Based Computer System
Patent: 6,765,795 →
Application: 10/200,803 →
Publication: US 2004/0017653
Method and Rack for Exchanging Air with Modular Bricks in a Computer System
Patent: 6,882,531 →
Application: 10/201,230 →
Publication: US 2004/0017655
Method and System for Renaming Registers in a Microprocessor
Patent: 7,406,587 →
Application: 10/210,257 →
Computer Enclosure and Method for Manufacture
Patent: 6,813,151 →
Application: 10/219,654 →
Electromagneric Interference Cable Backshell Assembly for High-Density Interconnect
Patent: 7,485,003 →
Application: 10/235,221 →
Publication: US 2004/0048516
System and Method for Hierarchical Approximation of Least Recently Used Replacement Algorithms Within a Cache Organized as Two or More Super-Ways of Memory Blocks
Patent: 6,986,001 →
Application: 10/274,766 →
Publication: US 2004/0078526
System and Method for Conveying Information
Patent: 7,712,006 →
Application: 10/310,237 →
Synchronization Circuits for the Distribution of Unique Data to Scattered Locations
Patent: 7,302,027 →
Application: 10/356,236 →
Publication: US 2004/0151270
Address Translation Using a Page Size Tag
Patent: 7,089,398 →
Application: 10/632,131 →
Publication: US 2005/0027961
System and Method for Encoding Page Size Information
Patent: 7,100,018 →
Application: 10/632,681 →
Publication: US 2005/0027962
Memory Access Management in a Shared Memory Multi-Processor System
Patent: 7,174,437 →
Application: 10/687,196 →
Publication: US 2005/0086439
Method and Apparatus for Maintaining Coherence Information in Multi-Cache Systems
Patent: 7,370,154 →
Application: 10/785,575 →
Publication: US 2005/0188160
Anticipatory Programmable Interface Pre-Driver
Patent: 7,327,167 →
Application: 11/116,734 →
Publication: US 2006/0244486
System for insertion and extraction of an electronic module
Patent: 7,466,561 →
Application: 11/261,045 →
Publication: US 2007/0097662
Generation and Use of System Level Defect Tables for Main Memory
Patent: 7,478,285 →
Application: 11/323,029 →
Publication: US 2007/0174718
System and Method for Reducing Back Flow
Patent: 7,425,117 →
Application: 11/343,968 →
Publication: US 2006/0194533
System and Method for Optimizing Computational Density
Patent: 7,603,573 →
Application: 11/585,619 →
Publication: US 2008/0155279
Computer Housing
Patent: 431,242 →
Application: 29/097,545 →
Bezel for a Computer
Patent: 429,248 →
Application: 29/108,315 →
Radial Computer System
Patent: 436,950 →
Application: 29/113,555 →
Drive sled handle
Patent: 444,471 →
Application: 29/125,872 →
Drive sled cover
Patent: 444,474 →
Application: 29/125,873 →
Front panel media door
Patent: 445,425 →
Application: 29/125,876 →
Server door
Patent: 445,112 →
Application: 29/127,551 →
Server cover
Patent: 444,461 →
Application: 29/127,590 →
Panel
Patent: 464,973 →
Application: 29/135,733 →
Panel
Patent: 464,054 →
Application: 29/135,803 →
Industrial Rack
Patent: 463,796 →
Application: 29/136,032 →
Server Product Faceplate
Patent: 464,056 →
Application: 29/146,729 →
Set of Multi Device Faceplates
Patent: 473,561 →
Application: 29/148,943 →
Related Assignments (19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 18, 2014
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 032714/0032 →
Change of Name Apr 18, 2014
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 032714/0230 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests... Apr 24, 2014
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0847 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests... Apr 24, 2014
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0001 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests... Apr 24, 2014
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0467 →
Merger Apr 24, 2014
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 032758/0516 →
Merger Jan 28, 2015
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 034837/0218 →
Security Interest Mar 13, 2015
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035200/0722 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests. . . Jul 25, 2016
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS INC
Reel/Frame 039461/0765 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests. Jul 25, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039461/0713 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 25, 2016
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 039461/0522 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 26, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039482/0015 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 26, 2016
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 039474/0606 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests Jul 27, 2016
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC
Reel/Frame 039484/0869 →
Change of Name Aug 9, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 039636/0809 →
Assignment of Assignor's Interest Oct 21, 2016
From: CRAY RESEARCH, L.L.C.
To: SILICON GRAPHICS, INC.
Reel/Frame 040092/0651 →
Merger Oct 21, 2016
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 040464/0893 →
Release of Security Interest Nov 2, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS AGENT
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040545/0362 →
Assignment of Assignor's Interest Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →