Method and system for estimating interconnect delay
View Patent ↗A system and method for estimating interconnect delay are disclosed that include determining inductance of an interconnect. A transfer function is determined using the inductance, and two poles of the transfer function are determined. An interconnect delay is estimated using the two poles.
1. A method for estimating interconnect delay, the method comprising:
determining an interconnect inductance of an interconnect;
determining a transfer function using the interconnect inductance;
determining at least two poles of the transfer function;
estimating an interconnect response using the two poles, the interconnect response describing a reaction of the interconnect to an applied signal; and
estimating an interconnect delay from the interconnect response, the interconnect delay describing a delay of the interconnect.
2. The method of claim 1 , further comprising:
determining a damping case from the two poles; and
estimating the interconnect delay according to the damping case.
3. The method of claim 1 , further comprising:
determining an overdamped case from the two poles; and
estimating the interconnect delay using one pole.
4. The method of claim 1 , further comprising:
determining an underdamped case from the two poles; and
estimating the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable.
5. The method of claim 1 , further comprising:
determining an underdamped case from the two poles; and
estimating the interconnect delay by repeating the following:
computing a current delay; and
computing a next delay using the current delay as a value for a time variable, until a difference between the current delay and the next delay is within a predetermined range.
6. The method of claim 1 , further comprising:
determining a critically damped case from the two poles; and
estimating the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable.
7. The method of claim 1 , further comprising:
determining a critically damped case from the two poles; and
estimating the interconnect delay by repeating the following:
computing a current delay, and
computing a next delay using the current delay as a value for a time variable, until a difference between the current delay and the next delay is within a predetermined range.
8. A system for estimating interconnect delay, the system comprising:
a memory operable to store information about an interconnect; and
a processor coupled to the memory operable to:
determine an interconnect inductance of the interconnect from the information;
determine a transfer function using the interconnect inductance;
determine at least two poles of the transfer function;
estimate an interconnect response using the two poles, the interconnect response describing a reaction of the interconnect to an applied signal; and
estimate an interconnect delay from the interconnect response, the interconnect delay describing a delay of the interconnect.
9. The system of claim 8 , wherein the processor is operable to:
determine a damping case from the two poles; and
estimate the interconnect delay according to the damping case.
10. The system of claim 8 , wherein the processor is operable to:
determine an overdamped case from the two poles; and
estimate the interconnect delay from one pole.
11. The system of claim 8 , wherein the processor is operable to:
determine an underdamped case from the two poles; and
estimate the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable.
12. The system of claim 8 , wherein the processor is operable to:
determine an underdamped case from the two poles; and
estimate the interconnect delay by repeating the following:
computing a current delay; and
computing a next delay using the current delay as a value for a time variable, until a difference between the current delay and the next delay is within a predetermined range.
13. The system of claim 8 , wherein the processor is operable to:
determine a critically damped case from the two poles; and
estimate the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable.
14. The system of claim 8 , wherein the processor is operable to:
determine a critically damped case from the two poles; and
estimate the interconnect delay by repeating the following:
computing a current delay; and
computing a next delay using the current delay as a value for a time variable, until a difference between the current delay and the next delay is within a predetermined range.
15. Logic for estimating interconnect delay encoded on media, the logic embodied in a medium and operable to:
determine an interconnect inductance of an interconnect;
determine a transfer function using the interconnect inductance;
determine at least two poles of the transfer function;
estimate an interconnect response using the two poles, the interconnect response describing a reaction of the interconnect to an applied signal; and
estimate an interconnect delay from the interconnect response, the interconnect delay describing a delay of the interconnect.
16. The logic of claim 15 , the logic operable to:
determine a damping case from the two poles; and
estimate the interconnect delay according to the damping case.
17. The logic of claim 15 , the logic operable to:
determine an overdamped case from the two poles; and
estimate the interconnect delay using one pole.
18. The logic of claim 15 , the logic operable to:
determine an underdamped case from the two poles; and
estimate the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable.
19. The logic of claim 15 , the logic operable to:
determine an underdamped case from the two poles; and
estimate the interconnect delay by repeating the following:
computing a current delay; and
computing a next delay using the current delay as a value for a time variable, until a difference between the current delay and the next delay is within a predetermined range.
20. The logic of claim 15 , the logic operable to:
determine a critically damped case from the two poles; and
estimate the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable.
21. The logic of claim 15 , the logic operable to:
determine a critically damped case from the two poles; and
estimate the interconnect delay by repeating the following:
computing a current delay; and
computing a next delay using the current delay as a value for a time variable, until a difference between the current delay and the next delay is within a predetermined range.
22. A system for estimating interconnect delay, the system comprising:
an inductance module operable to determine an interconnect inductance of an interconnect;
a transfer function module operable to determine a transfer function using the interconnect inductance;
a processor operable to:
determine at least two poles of the transfer function;
determine a damping case from the two poles, the damping case comprising an overdamped case, an underdamped case, and a critically damped case;
a response module operable to estimate an interconnect response using the two poles, the interconnect response describing a reaction of the interconnect to an applied signal; and
a delay module operable to:
estimate the interconnect delay from one pole, if the damping case is the overdamped case, the interconnect delay describing a delay of the interconnect;
estimate the interconnect delay by:
computing a first delay using an Elmore delay; and
computing a second delay using the first delay as a value for a time variable, if the damping case is the underdamped case or the critically damped case.