Anticipatory programmable interface pre-driver
View Patent ↗This document discusses, among other things, a circuit for selectively engaging an output section based on a received data signal. The output is driven to a high-impedance state in anticipation of a possible change in driving agent. An output section includes active transistor elements and a pre-driver.
1. A method comprising:
receiving a data input signal;
generating an output enable signal for a driver, the output enable signal based on the data input signal;
driving a bus to a particular logic level using the driver, the logic level based on a driver input and based on the output enable signal, wherein the driver input is provided to the driver, and the driver input is based on the data input signal; and
setting the bus to a high impedance state by toggling the output enable signal; and wherein a time delay between receiving the data input signal and generating the output enable signal is less than a time delay between receiving the data input signal and providing the driver input.
2. The method of claim 1 wherein generating the output enable signal includes executing a logical or function with the data input signal.
3. The method of claim 1 wherein generating the output enable signal includes receiving a bypass signal, and wherein the bypass signal is logically ANDed with the data input signal.
4. The method of claim 1 further including setting the bus to the high impedance state prior to driving the bus to the particular logic level.
5. A system comprising:
an output section having an output enable node, a level node and a pad node;
a inverter having an output coupled to the level node;
a logical OR gate having an OR output node coupled to the output enable node;
a first flip flop having a Q 1 output coupled to a first input of the logical OR gate;
a logical AND gate having an AND output node coupled to a second input of the logical OR gate;
a second flip flop having a Q 0 output coupled to an input of the first flip flop, an input of the inverter and a third input of the logical OR gate;
a data input node coupled to an input of the second flip flop and a first input of the logical AND gate;
a bypass node coupled to a second input of the logical AND gate;
a first clock coupled to a second input of the second flip flop; and
a second clock coupled to a second input of the first flip flop.
6. The system of claim 5 further including a delay line coupled between the data input node and the first input of the logical AND gate.
7. The system of claim 6 wherein the delay line is adjustable.
8. The system of claim 5 further including an impedance controller coupled to the output section.
9. The system of claim 5 wherein at least one of the first flip flop and the second flip flop include a JK flip flop.
10. The method of claim 1 wherein generating the output enable signal includes executing combinatorial logic having inputs including a clock and the data input signal.
11. The method of claim 1 wherein generating the output enable signal is independent of the particular logic level generated by the driver.
12. The method of claim 3 wherein receiving the bypass signal includes configuring the bypass signal based on a clock speed.