IP Library Granted Patent US 7,765,454
Granted Patent B2
US 7,765,454 · App. 11/136,260 · Granted Jul 27, 2010

Fault tolerant memory system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,765,454
App. No.
11/136,260
Granted
Jul 27, 2010
Kind
B2
Abstract

A method and apparatus for managing X4 or larger types of memory first receives a data word to be stored in the memory, and then generates a check datum, which is a function of the data word and a set of encode data. After storing the data word in memory, the method and apparatus use the check datum and the data word to generate a syndrome. The method and apparatus then determine if the data word in the memory is correct as a function of the syndrome.

Claims (64)

1. A method of managing X4 or larger types of memory, the method comprising:

receiving a data word to be stored in the memory;

producing a set of encode data;

generating a 16-bit check datum as a function of the data word to be stored and the encode data;

storing the data word in the memory;

using the check datum and the data word in the memory to generate a 16-bit syndrome;

determining if the data word in the memory is correct as a function of the syndrome; and

if the data word in the memory is not correct as a function of the syndrome, correcting between two and eight non-adjacent bits in the data word.

2. The method as defined by claim 1 further including storing the check datum in memory.

3. The method as defined by claim 1 wherein generating a check datum includes applying a function to selected bits of the data word, the selected bits being selected as determined by the set of encode data.

4. The method as defined by claim 1 wherein using the check datum includes:

appending the check datum with the data word to produce revised data; and

applying a logical function to selected bits of the revised data to produce the syndrome, the selected bits being selected as determined by the set of encode data to produce the syndrome.

5. The method as defined by claim 1 wherein determining if the data word in the memory is correct includes:

comparing the syndrome to a set of error identity data; and

determining that the data word in the memory is not correct if the syndrome matches at least one datum in the set of error identity data.

6. The method as defined by claim 5 wherein the set of error identity data is generated from the set of encode data, the set of error identity data including a plurality of values assigned to each bit of the data word, the error of a given bit being corrected if the syndrome matches at least one of the plurality of values assigned to the given bit.

7. The method as defined by claim 1 wherein the set of encode data includes a table identifying bits of the data word to be processed.

8. The method as defined by claim 1 further comprising:

determining that a given bit of the data word has an error; and

re-reading the given bit to determine if the error has been corrected.

9. The method as defined by claim 8 further comprising:

storing the data word in a mirror memory location; and

if the given bit is determined to have the error after it is re-read, then retrieving the correct data for the given bit from the mirror memory location and storing that corrected data in the given bit.

10. The method as defined by claim 8 further including correcting other bit errors in the data word if the given bit is corrected.

11. A computer program product for use on a computer system for managing X4 or larger types of memory, the computer program product comprising a tangible computer usable medium having computer readable program code thereon, the computer readable program code comprising:

program code for receiving a data word to be stored in the memory;

program code for producing a set of encode data;

program code for generating a 16-bit check datum as a function of the data word to be stored and the encode data;

program code for storing the data word in the memory;

program code for using the check datum and the data word in the memory to generate a 16-bit syndrome;

program code for determining if the data word in the memory is correct as a function of the syndrome; and

program code for correcting between two and eight non-adjacent bits in the data word if the data word in the memory is not correct as a function of the syndrome.

12. The computer program product as defined by claim 11 further including program code for storing the check datum in memory.

13. The computer program product as defined by claim 11 wherein the program code for generating a check datum includes program code for applying a function to selected bits of the data word, the selected bits being selected as determined by the set of encode data.

14. The computer program product as defined by claim 11 wherein the program code for using the check datum includes:

program code for appending the check datum with the data word to produce revised data; and

program code for applying a logical function to selected bits of the revised data to produce the syndrome, the selected bits being selected as determined by the set of encode data to produce the syndrome.

15. The computer program product as defined by claim 11 wherein the program code for determining if the data word in memory is correct includes:

program code for comparing the syndrome to a set of error identity data; and

program code for determining that the data word in the memory is not correct if the syndrome matches at least one datum in the set of error identity data.

16. The computer program product as defined by claim 15 wherein the set of error identity data is generated from the set of encode data, the set of error identity data including a plurality of values assigned to each bit of the data word, the error of a given bit being corrected if the syndrome matches at least one of the plurality of values assigned to the given bit.

17. The computer program product as defined by claim 11 wherein the set of encode data includes a table identifying bits of the data word to be processed.

18. The computer program product as defined by claim 11 further comprising:

program code for determining that a given bit of the data word has an error; and

program code for re-reading the given bit to determine if the error has been corrected.

19. The computer program product as defined by claim 18 further comprising:

program code for storing the data word in a mirror memory location; and

program code for retrieving the correct data for the given bit from the mirror memory location and storing that corrected data in the given bit.

20. The computer program product as defined by claim 18 further including program code for correcting other bit errors in the data word if the given bit is corrected.

21. An apparatus for managing X4 or larger types of memory, the apparatus comprising:

an input for receiving a data word to be stored in the memory;

an encoder operatively coupled with the input, the encoder generating a 16-bit check datum as a function of the data word to be stored and a set of encode data;

a data handler operatively coupled with the memory, the data handler storing the data word in the memory;

a decoder that uses the check datum and the data word in the memory to generate a 16-bit syndrome; and

an error module for determining if the data word in the memory is correct as a function of the syndrome and correction between two and eight non-adjacent bits in the data word.

22. The apparatus as defined by claim 21 wherein the encoder is configured to apply a function to selected bits of the data word, the selected bits being selected as determined by the set of encode data.

23. The apparatus as defined by claim 21 wherein the error module includes:

a comparator for comparing the syndrome to a set of error identity data; and

a corrector for correcting the error if the syndrome matches at least one datum in the set of error identity data, the corrector being configured to correct between one and four bits of data.

24. The apparatus as defined by claim 23 wherein the set of error identity data is generated from the set of encode data, the set of error identity data including a plurality of values assigned to each bit of the data word, the error of a given bit being corrected if the syndrome matches at least one of the plurality of values assigned to the given bit.

25. The apparatus as defined by claim 21 wherein if the error module determines that a given bit of the data word has an error, then it re-reads the given bit to determine if the error has been corrected.

26. The apparatus as defined by claim 25 wherein the data word is stored in a mirror memory location, and if the given bit is determined to have the error after it is re-read, then the error module is configured to retrieve the correct data for the given bit from the mirror memory location and store that corrected data in the given bit.

27. The apparatus as defined by claim 25 wherein the error module is configured to correct other bit errors in the data word if the given bit is corrected.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS AGENT
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040545/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2016
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 039465/0001 →
CHANGE OF NAME Recorded Jul 26, 2016
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 039465/0390 →
ORDER...AUTHORIZING THE SALE OF ALL OR SUBSTANTIALLY ALL OF THE ASSETS OF THE DEBTORS FREE AND CLEAR OF ALL LIENS, ENCUMBRANCES, AND INTERESTS. Recorded Jul 26, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039482/0015 →
MERGER Recorded Jul 26, 2016
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 039257/0994 →
SECURITY INTEREST Recorded Mar 13, 2015
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035200/0722 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2012
From: SILICON GRAPHICS, INC. ET AL.; SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL, CORP.
Reel/Frame 027904/0315 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2007
From: GENERAL ELECTRIC CAPITAL CORPORATION
To: MORGAN STANLEY & CO., INCORPORATED
Reel/Frame 019995/0895 →
SECURITY INTEREST Recorded Oct 24, 2006
From: SILICON GRAPHICS, INC.
To: GENERAL ELECTRIC CAPITAL CORPORATION
Reel/Frame 018545/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2005
From: PASSINT, RANDAL S.
To: SILICON GRAPHICS, INC.
Reel/Frame 016606/0946 →