IP Library Granted Patent US 9,240,940
Granted Patent B2
US 9,240,940 · App. 13/843,919 · Granted Jan 19, 2016

Scalable infiniband interconnect performance and diagnostic tool

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Quick Facts
Patent No.
US 9,240,940
App. No.
13/843,919
Granted
Jan 19, 2016
Kind
B2
Abstract

In accordance with some implementations, a method for evaluating large scale computer systems based on performance is disclosed. A large scale, distributed memory computer system receives topology data, wherein the topology data describes the connections between the plurality of switches and lists the nodes associated with each switch. Based on the received topology data, the system performs a data transfer test for each of the pair of switches. The test includes transferring data between a plurality of nodes and determining a respective overall test result value reflecting overall performance of a respective pair of switches for a plurality of component tests. The system determines that the pair of switches meets minimum performance standards by comparing the overall test result value against an acceptable test value. If the overall test result value does not meet the minimum performance standards, the system reports the respective pair of switches as underperforming.

Claims (32)

1. A method for evaluating the performance of large scale computer systems, the method comprising:

receiving topology data at a large scale distributed memory computer system, wherein the topology data describes the connections between a plurality of switches, each switch connected to a plurality of nodes, and the topology data lists each node of the plurality of nodes that is associated with each switch of the plurality of switches;

performing a data transfer test for each of a pair of switches based on the received topology data for each pair of switches in the plurality of switches, wherein each of the pair of switches includes a first switch and a second switch that connect to each other via direct links, the first and the second switch grouped as a pair when preparing to perform the data transfer test, and each switch is included in only one of the pair of switches at a time;

transferring data between a plurality of nodes associated with a first switch in a pair of switches and a plurality of nodes associated with a second switch in the pair of switches;

determining a respective overall test result value reflecting overall performance of a respective pair of switches for a plurality of component tests, wherein the component tests reflect performance of links between switches and performance nodes connected to the switches during the transfer of data;

determining that the pair of switches meets minimum performance standards by comparing the overall test result value against an acceptable test value; and

reporting the respective pair of switches as underperforming in accordance with a determination that the overall test result value does not meet the minimum performance standards.

2. The method of claim 1 , further comprising:

performing an additional data transfer test for each node connected to either the first switch or the second switch and for each link between the first switch and the second switch, wherein a link is a direct connection from a single port of the first switch and a single port of the second switch;

determining whether one or more of the nodes or one or more of the link between the first switch and the second switch is a point of failure based on the additionally performed data transfer test; and

storing data identifying the determined point of failure in accordance with a determination that a respective node or link is a point of failure.

3. The method of claim 2 , further comprising:

determining that network routing imbalance is the point of failure in accordance with a determination that none of the nodes or links are a point of failure; and

storing data identifying network routing imbalance as the point of failure in accordance with a determination that network routing imbalance is the point of failure.

4. The method of claim 1 , wherein data transfer tests for each pair of switches are performed concurrently.

5. The method of claim 1 , wherein the data transfer test is a bi-directional test between a plurality of nodes associated with a first switch in a pair of switches and all nodes associated with a second switch in a pair of switches.

6. The method of claim 1 , wherein the data transfer test includes transferring a predetermined amount of data from a first node connected to the first switch in the respective pair of switches to a second node connected to the second switch in the respective pair of switches.

7. The method of claim 6 wherein the overall test result value represents the amount of data transferred per unit time.

8. The method of claim 1 , wherein the data transfer test includes transferring data from a first node connected to the first switch in the respective pair of switches to a second node connected to the second switch in the respective pair of switches for a predetermined amount of time.

9. The method of claim 1 , wherein an acceptable performance standard test value is predetermined.

10. The method of claim 1 , wherein the acceptable performance standard test value is based on a median test result value for the respective pair of switches.

11. The method of claim 1 , wherein each switch in the plurality of switches has N connections to other switches and each connection for a respective switch is associated with a dimension of an N-dimension hypercube network.

12. The method of claim 11 , further comprising:

grouping each switch in the plurality of switches into a pair of switches based on the switch connection associated with the respective dimension of the hypercube for each respective dimension of the N-dimensions; and

concurrently performing all pair-wise bidirectional transfers tests for all pair of switches in the respective dimension, wherein the dimensions are tested sequentially.

13. A non-transitory computer readable storage medium having embodied thereon a program executable by a processor to perform a method for evaluating the performance of large scale computer systems, the method comprising:

receiving topology data at a large scale distributed memory computer system, wherein the topology data describes the connections between a plurality of switches, each switch connected to a plurality of nodes, and the topology data lists each node of the plurality of nodes that is associated with each switch of the plurality of switches;

performing a data transfer test for each of a pair of switches based on the received topology data for each pair of switches in the plurality of switches, wherein each of the pair of switches includes a first switch and a second switch that connect to each other via direct links, the first and the second switch grouped as a pair when preparing to perform the data transfer test, and each switch is included in only one of the pair of switches at a time;

transferring data between a plurality of nodes associated with a first switch in a pair of switches and a plurality of nodes associated with a second switch in the pair of switches;

determining a respective overall test result value reflecting overall performance of a respective pair of switches for a plurality of component tests, wherein the component tests reflect performance of links between switches and performance nodes connected to the switches during the transfer of data;

determining that the pair of switches meets minimum performance standards by comparing the overall test result value against an acceptable test value; and

reporting the respective pair of switches as underperforming in accordance with a determination that the overall test result value does not meet the minimum performance standards.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS AGENT
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040545/0362 →
SECURITY INTEREST Recorded May 10, 2016
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038532/0574 →
SECURITY INTEREST Recorded Mar 13, 2015
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035200/0722 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2013
From: BARON, JOHN
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 031311/0204 →