IP Library Granted Patent US 8,433,816
Granted Patent B2
US 8,433,816 · App. 12/121,941 · Granted Apr 30, 2013

Network topology for a scalable multiprocessor system

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Quick Facts
Patent No.
US 8,433,816
App. No.
12/121,941
Granted
Apr 30, 2013
Kind
B2
Abstract

A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

Claims (13)

1. A massively parallel processing system comprising:

a scalable interconnection network comprising:

a plurality of first level routers for interconnecting a plurality of processing elements nodes in a cluster; and

one or more metarouters for interconnecting the plurality of first level routers so that each one of the first level routers in a first cluster is connected to all other clusters through one or more metarouters, wherein if one of the metarouters is coupled to one of the first level routers, then the one of the metarouters is also coupled to less than two other metarouters, otherwise the one of the metarouters is coupled to two metarouters.

2. The massively parallel processing system of claim 1 wherein each one of the clusters is a two-dimensional hypercube.

3. The massively parallel processing system of claim 1 wherein each one of the metaroutes are eight port routers.

4. The massively parallel processing system of claim 1 wherein each one of the metarouters are four port routers.

5. The massively parallel processing system of claim 1 wherein each one of the processing element nodes comprises four processors.

6. A massively parallel processing system processing:

a plurality of processors:

a first set of routers for interconnecting the plurality of processors as two-dimensional hypercubes;

a second set of routers for interconnecting the first set of routers where the hypercubes remain intact as the system is expanded; and

wherein the second set of routers includes at least one router that is coupled to two other routers in the second set of routers, and wherein the at least one router is not coupled to any router in the first set of routers.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS AGENT
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040545/0362 →
SECURITY INTEREST Recorded Mar 13, 2015
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035200/0722 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2014
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 032692/0491 →
MERGER Recorded Apr 16, 2014
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 032692/0663 →
CHANGE OF NAME Recorded Apr 16, 2014
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 032706/0679 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2014
From: DENEROFF, MARTIN M.; THORSON, GREGORY M.; PASSINT, RANDAL S.
To: SILICON GRAPHICS, INC.
Reel/Frame 031876/0142 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2012
From: SILICON GRAPHICS, INC. ET AL.; SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL, CORP.
Reel/Frame 027904/0315 →
SECURITY AGREEMENT Recorded Dec 16, 2008
From: SILICON GRAPHICS, INC.
To: MORGAN STANLEY & CO., INCORPORATED
Reel/Frame 021985/0269 →