Method and system for managing memory in a multiprocessor system
View Patent ↗A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.
1. A multiprocessor system for managing memory among a plurality of processors, comprising:
a processor layer including a plurality of processors, the plurality of processors being grouped into a plurality of processor coherence domains, the plurality of processors operable to directly communicate with each other, wherein only processors within a particular processor coherence domain coherently share data;
an input/output layer including a plurality of input/output nodes, each input/output node operable to directly communicate with each other;
a network layer including a plurality of router nodes operable to provide communication with and between the processor layer and the input/output layer, the plurality of router nodes operable to communicate directly with each other, wherein only certain input/output nodes and routers coherently share data with those processors of the particular processor coherence domain.
2. The multiprocessor system of claim 1 , wherein each processor is operable to obtain an exclusive copy of a cache line regardless of which processor coherence domain in which the cache line resides.
3. The multiprocessor system of claim 1 , wherein each processor includes an identifier indicating in which processor coherence domain they reside.
4. The multiprocessor system of claim 1 , wherein a particular processor coherence domain may operate on an operating system different than an operating system of another processor coherence domain.
5. The multiprocessor system of claim 1 , wherein requests to share data in a memory associated with a processor in a particular processor coherence domain is denied to processors in other processor coherence domains.
6. The multiprocessor system of claim 1 , wherein a particular processor coherence domain includes a sharing vector independent of sharing vectors in other processor coherence domains, the sharing vector operable to track a location of shared copies of data.
7. The multiprocessor system of claim 6 , wherein any input/output node may have exclusive access to data without being tracked in any sharing vector.
8. The multiprocessor system of claim 7 , wherein an input/output node may have exclusive access to data for a predetermined period of time.
9. The multiprocessor system of claim 8 , wherein the data is invalidated at the input/output node upon expiration of the predetermined period of time.
10. The multiprocessor system of claim 8 , wherein the data is indicated as being unowned upon expiration of the predetermined period of time.
11. A method for managing memory in a multiprocessor system, comprising:
defining a plurality of processor coherence domains within a system coherence domain of a multiprocessor system, the processor coherence domains each including a plurality of processors and a processor memory;
defining a plurality of input/output nodes, each input/output node operable to directly communicate with each other;
defining a plurality of router nodes operable to provide communication with and between the processor layer and the input/output layer, the plurality of router nodes operable to communicate directly with each other;
providing shared access to data in the processor memory of a particular processor coherence domain only to elements of the multiprocessor system within the particular processor coherence domain and certain input/output nodes and routers associated with the particular processor coherence domain.
12. The method of claim 11 , further comprising:
obtaining an exclusive copy of a cache line regardless of which processor coherence domain in which they reside.
13. The method of claim 11 , further comprising:
providing an identifier in each processor to indicate in which processor coherence domain they reside.
14. The method of claim 11 , further comprising:
operating a particular processor coherence domain on an operating system different than an operating system of another processor coherence domain.
15. The method of claim 11 , further comprising:
defining a sharing vector for each processor coherence domain, each sharing vector being independent of sharing vectors in other processor coherence domains, the sharing vector operable to track a location of shared copies of data.
16. A system for managing memory in a multiprocessor system, comprising:
means for defining a plurality of processor coherence domains within a system coherence domain of a multiprocessor system, the processor coherence domains each including a plurality of processors and a processor memory;
means for defining a plurality of input/output nodes, each input/output node operable to directly communicate with each other;
means for defining a plurality of router nodes operable to provide communication with and between the processor layer and the input/output layer, the plurality of router nodes operable to communicate directly with each other;
means for providing shared access to data in the processor memory of a particular processor coherence domain only to elements of the multiprocessor system within the particular processor coherence domain and certain input/output nodes and routers associated with the particular processor coherence domain.
17. The system of claim 16 , further comprising:
means for obtaining an exclusive copy of a cache line regardless of which processor coherence domain in which they reside.
18. The method of claim 16 , further comprising:
means for providing an identifier in each processor to indicate in which processor coherence domain they reside.
19. The method of claim 16 , further comprising:
means for operating a particular processor coherence domain on an operating system different than an operating system of another processor coherence domain.
20. The method of claim 16 , further comprising:
means for defining a sharing vector for each processor coherence domain, each sharing vector being independent of sharing vectors in other processor coherence domains, the sharing vector operable to track a location of shared copies of data.