IP Library Granted Patent US 8,812,765
Granted Patent B2
US 8,812,765 · App. 13/848,546 · Granted Aug 19, 2014

Data coherence method and apparatus for multi-node computer system

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Quick Facts
Patent No.
US 8,812,765
App. No.
13/848,546
Granted
Aug 19, 2014
Kind
B2
Abstract

A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more blocks and stores a data record for each block indicating a plurality of node groups and a selection of the node groups. Each selected node group represents a number of nodes, and selected node groups represent at least one node that has requested access to the block. In response to receiving an access request from a requesting node that may or may not be in a selected node group, the method and system update the data record to indicate the correct selection. If the requesting node is not in any node group, the data record is adjusted to have new node groups, one of which represents the requesting node.

Claims (31)

1. A method of maintaining the coherency of a local memory of a given processing node in a non-uniform memory architecture computer system having a plurality of processing nodes, each processing node including at least one computing processor and a local memory, wherein a subset of the computing processors cooperate on a common task, the method comprising:

dividing the local memory of the given node into one or more blocks;

in the local memory of the given processing node, storing a data record for each block of memory in the one or more blocks, each data record comprising:

data indicating a plurality of node groups, each node group representing a number of nodes in the plurality of processing nodes, and

data indicating a selection of node groups in the plurality of node groups, each selected node group representing at least one processing node that has requested access to the block of memory; and

in response to receiving a request from a requesting processing node to access a block of memory in the given processing node, indicating, in the data record associated with the requested block of memory, a selection of node groups representing at least 1) the nodes already represented by the selection of node groups and 2) the requesting processing node.

2. The method as defined by claim 1 , wherein responsively indicating the selection of node groups comprises:

forming a first plurality of new node groups by combining pairs of node groups;

forming a second plurality of new node groups, at least one node group in the second plurality of new node groups representing the requesting processing node; and

forming the new data record from the first and second pluralities of new node groups, wherein each new node group represents the same number of processing nodes in the plurality of processing nodes.

3. The method as defined by claim 2 , wherein forming the first plurality of new node groups includes combining pairs of node groups whose represented processing nodes are relative neighbors within the computer system.

4. The method as defined by claim 1 , wherein each node group represents a number of processing nodes equal to the number one, or a power of two.

5. The method as defined by claim 1 , further comprising forwarding a coherence message to at least one of the processing nodes in the node group representing the requesting processing node, the coherence message having information relating to the state of the requested block.

6. The method as defined by claim 1 , wherein the data record uses a multi-dimensional data structure to indicate the plurality of node groups.

7. The method as defined by claim 1 , wherein the data record uses a string of bits to indicate the selection of node groups.

8. A non-uniform memory architecture shared-memory computer system having a plurality of processing nodes, each node comprising:

at least one computing processor;

a memory, coupled to the at least one computing processor, wherein a subset of the computing processors in different processing nodes of the computer system cooperate on a common task; and

a directory controller, coupled to the at least one computing processor and the memory, the directory controller being configured to store in the memory, for each block of memory in the one or more blocks, a data record comprising:

data indicating a plurality of node groups, each node group representing a number of nodes in the plurality of processing nodes, and

data indicating a selection of node groups in the plurality of node groups, each selected node group representing at least one processing node that has requested access to the block of memory;

wherein the directory controller is configured to receive a request from a requesting processing node to access a block of the memory, and to responsively indicate, in the data record associated with the requested block of the memory, a selection of node groups representing at least 1) the nodes already represented by the selection of node groups and 2) the requesting processing node.

9. The system as defined by claim 8 , wherein responsively indicating the selection of node groups comprises:

forming a first plurality of new node groups by combining pairs of node groups;

forming a second plurality of new node groups, at least one node group in the second plurality of new node groups representing the requesting processing node; and

forming the new data record from the first and second pluralities of new node groups, wherein each new node group represents the same number of processing nodes in the plurality of processing nodes.

10. The system as defined by claim 9 , wherein forming the first plurality of new node groups includes combining pairs of node groups whose represented processing nodes are relative neighbors within the computer system.

11. The system as defined by claim 8 , wherein each node group represents a number of processing nodes equal to the number one, or a power of two.

12. The system as defined by claim 8 , wherein the directory controller is further configured to forward a coherence message to at least one of the processing nodes in the node group representing the requesting processing node, the coherence message having information relating to the state of the requested block.

13. The system as defined by claim 8 , wherein the data record uses a multi-dimensional data structure to indicate the plurality of node groups.

14. The system as defined by claim 8 , wherein the data record uses a string of bits to indicate the selection of node groups.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS AGENT
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040545/0362 →
SECURITY INTEREST Recorded Mar 13, 2015
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035200/0722 →
CHANGE OF NAME Recorded Mar 26, 2013
From: SILICON GRAPHICS INTERNATIONAL, INC.
To: SGI INTERNATIONAL, INC.
Reel/Frame 030088/0713 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2013
From: DAI, DONGLAI; PASSINT, RANDAL
To: SILICON GRAPHICS, INC.
Reel/Frame 030082/0982 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2013
From: SILICON GRAPHICS, INC.
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 030086/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2013
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL, CORP.
Reel/Frame 030086/0259 →