System and method for performing memory operations in a computing system
View Patent ↗A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
1. A system for performing memory operations in a computing system, comprising:
a processor operable to operate in one of a plurality of operating states, the processor including a transaction record to track the plurality of operating states;
a cache memory operable to identify one of a plurality of cache states for each cache line stored therein, the plurality of cache states being associated with the plurality of operating states.
2. The system of claim 1 , wherein the processor is operable to function in a Normal operating state, the Normal operating state indicating that the processor is not involved in a memory transaction.
3. The system of claim 1 , wherein the processor is operable to function in a Transaction operating state, the Transaction operating state indicating that the processor is engaged with a memory transaction.
4. The system of claim 3 , wherein the processor prevents any changes to the memory while in the Transaction operating state.
5. The system of claim 1 , wherein the processor is operable to function in a Commit operating state, the Commit operating state indicating that the processor will make visible to other processors in the system any changes made to the memory.
6. The system of claim 5 , wherein the processor holds processing of all incoming coherency messages until the Commit operating state is terminated.
7. The system of claim 1 , wherein the processor is operable to function in an Abort operating state, the Abort operating state indicating that any changes to memory are to be discarded.
8. The system of claim 7 , wherein the processor holds processing of all incoming coherency messages until the Abort operating state is terminated.
9. The system of claim 1 , wherein the processor is operable to function in a Suspended operating state, the Suspended operating state indicating that a memory transaction has been aborted.
10. The system of claim 1 , wherein the cache memory includes a shared transactional, an exclusive transactional, and a dirty transactional cache state, these transactional cache states indicating a status of a cache line prior to providing the cache line to other processors.
11. A method for performing memory operations in a computing system, comprising:
receiving an instruction to access a memory location while in a Normal operating state;
transitioning to a Transaction operating state in response to the instruction;
transitioning a cache line associated with the memory location from a conventional MESI coherency protocol to one of a plurality of transactional coherency states associated with the Transaction operating state;
performing updates to the cache line associated with the memory location, the updates to the cache line not being visible to other processors in the computing system;
receiving a commit instruction;
transitioning to a Commit operating state;
making any changes to the cache line visible to other processors in the computing system;
transitioning the cache line from one of the plurality of transactional states to the conventional MESI protocol;
transitioning to the Normal operating state upon making changes to the cache line visible to other processors and performing the cache line transition.
12. The method of claim 11 , further comprising:
receiving an event causing an abort of the instruction;
transitioning to an Abort operating state in response to the event.
13. The method of claim 12 , further comprising:
discarding any changes made to the cache line;
transitioning the cache line associated with the memory location from one of a plurality of transactional coherency states associated with the Transaction operating state to the conventional MESI coherency protocol.
14. The method of claim 13 , further comprising:
transitioning to a Suspended operating state upon completion of the discarding of any changes to the cache line.
15. The method of claim 14 , further comprising:
receiving a commit instruction;
transitioning to the Normal operating state in response to the commit instruction.
16. A computer readable medium including code for performing memory operations in a computing system, the code operable to:
receive an instruction to access a memory location while in a Normal operating state;
transition to a Transaction operating state in response to the instruction;
transition a cache line associated with the memory location from a conventional MESI coherency protocol to one of a plurality of transactional coherency states associated with the Transaction operating state;
perform updates to the cache line associated with the memory location, the updates to the cache line not being visible to other processors in the computing system;
receive a commit instruction;
transition to a Commit operating state;
make any changes to the cache line visible to other processors in the computing system;
transition the cache line from one of the plurality of transactional states to the conventional MESI protocol;
transition to the Normal operating state upon making changes to the cache line visible to other processors and performing the cache line transition.
17. The computer readable medium of claim 16 , the code further operable to:
receive an event causing an abort of the instruction;
transition to an Abort operating state in response to the event.
18. The computer readable medium of claim 17 , wherein the code is further operable to:
discard any changes made to the cache line;
transition the cache line associated with the memory location from one of a plurality of transactional coherency states associated with the Transaction operating state to the conventional MESI coherency protocol.
19. The computer readable medium of claim 18 , wherein the code is further operable to:
transitioning to a Suspended operating state upon completion of the discarding of any changes to the cache line.
20. The computer readable medium of claim 19 , wherein the code is further operable to:
receiving a commit instruction;
transitioning to the Normal operating state in response to the commit instruction.